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Initial commit: component/cs2300cp-czzr

Ray ·4bda502b29 ·
2 files changed +199
README.mdadded+46
@@ -0,0 +1,46 @@+# CS2300CP-CZZR++**Cirrus Logic** · Clock Generators, PLLs, Frequency Synthesizers · MSOP-10++CS2300CP-CZZR from Cirrus Logic, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VD | power_in | Digital power supply input (3.1-3.5 V) for digital and analog sections. |+| 2 | GND | power_in | Ground reference. |+| 3 | CLK_OUT | output | PLL clock output providing low-jitter clock at 6-75 MHz. |+| 4 | AUX_OUT | output | Auxiliary output selectable as buffered CLK_IN, CLK_OUT, or lock indicator via register configuration. |+| 5 | CLK_IN | input | Frequency reference clock input (50 Hz-30 MHz) for Digital PLL. |+| 6 | FILTP | bidirectional | LC oscillator filter positive pin; connect 0.1 µF capacitor to FILTN for external supply filtering. |+| 7 | FILTN | bidirectional | LC oscillator filter negative pin; connect 0.1 µF capacitor to FILTP and tie to GND. |+| 8 | AD0/CS | input | Address/chip select input; I²C mode via permanent connection to VD or GND, SPI mode via high-to-low transition after power-up. |+| 9 | SCL/CCLK | input | Serial clock input; 100 kHz maximum (I²C) or 6 MHz maximum (SPI). |+| 10 | SDA/CDIN | bidirectional | Serial data line; bidirectional in I²C mode (SDA) or input-only in SPI mode (CDIN) with open-drain driver. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Cirrus Logic |+| Package | MSOP-10 |+| Category | Clock/Timing |+| Pins | 10 |++## CAD (KiCad official)++- Symbol: `CS2300CP-CZZR`+- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`+- 3D model: MSOP-10 (KiCad packages3D, STEP)+- 3D model files: `cs2300cp-czzr-etched.step` / `cs2300cp-czzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cs2300cp-czzr.step` / `cs2300cp-czzr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Cirrus Logic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590155685980626944) (32 pp, sha256 `2938c833dd2affd8`, retrieved 2026-09-21, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cs2300cp-czzr-datasheet.pdf)
page.jsonadded+153
@@ -0,0 +1,153 @@+{+  "slug": "cs2300cp-czzr",+  "version": "0.1.0",+  "type": "component",+  "description": "Cirrus Logic Clock Generators, PLLs, Frequency Synthesizers, MSOP-10. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "clock-timing",+    "cs2300cp-czzr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cs2300cp-czzr.kicad_sym",+    "cs2300cp-czzr.kicad_mod",+    "cs2300cp-czzr.glb",+    "cs2300cp-czzr.step",+    "cs2300cp-czzr.lbr",+    "docs/hero.png",+    "docs/cs2300cp-czzr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "CS2300CP-CZZR",+    "manufacturer": "Cirrus Logic",+    "package": "MSOP-10",+    "pin_count": 10,+    "category": "Clock/Timing",+    "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590155685980626944",+    "parts": {+      "symbol": "cs2300cp-czzr.kicad_sym",+      "footprint": "cs2300cp-czzr.kicad_mod",+      "model_3d": "cs2300cp-czzr-etched.glb",+      "model_3d_plain": "cs2300cp-czzr.glb",+      "model_3d_step": "cs2300cp-czzr-etched.step",+      "model_3d_step_plain": "cs2300cp-czzr.step",+      "lbr": "cs2300cp-czzr.lbr"+    },+    "distributor_links": {+      "lcsc": "C2663260"+    },+    "pins": [+      {+        "number": "1",+        "name": "VD",+        "type": "power_in",+        "description": "Digital power supply input (3.1-3.5 V) for digital and analog sections."+      },+      {+        "number": "2",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference."+      },+      {+        "number": "3",+        "name": "CLK_OUT",+        "type": "output",+        "description": "PLL clock output providing low-jitter clock at 6-75 MHz."+      },+      {+        "number": "4",+        "name": "AUX_OUT",+        "type": "output",+        "description": "Auxiliary output selectable as buffered CLK_IN, CLK_OUT, or lock indicator via register configuration."+      },+      {+        "number": "5",+        "name": "CLK_IN",+        "type": "input",+        "description": "Frequency reference clock input (50 Hz-30 MHz) for Digital PLL."+      },+      {+        "number": "6",+        "name": "FILTP",+        "type": "bidirectional",+        "description": "LC oscillator filter positive pin; connect 0.1 µF capacitor to FILTN for external supply filtering."+      },+      {+        "number": "7",+        "name": "FILTN",+        "type": "bidirectional",+        "description": "LC oscillator filter negative pin; connect 0.1 µF capacitor to FILTP and tie to GND."+      },+      {+        "number": "8",+        "name": "AD0/CS",+        "type": "input",+        "description": "Address/chip select input; I²C mode via permanent connection to VD or GND, SPI mode via high-to-low transition after power-up."+      },+      {+        "number": "9",+        "name": "SCL/CCLK",+        "type": "input",+        "description": "Serial clock input; 100 kHz maximum (I²C) or 6 MHz maximum (SPI)."+      },+      {+        "number": "10",+        "name": "SDA/CDIN",+        "type": "bidirectional",+        "description": "Serial data line; bidirectional in I²C mode (SDA) or input-only in SPI mode (CDIN) with open-drain driver."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-4-6",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 32,+        "cost_usd": 0.2491,+        "at": "2026-09-21T19:04:22"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590155685980626944",+        "pages": 32,+        "sha256": "2938c833dd2affd8",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 10,+        "described": 10,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file