Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	4h ago
viewers	cs1231-ts: viewers · Ray	3h ago
cs1231-ts-etched.glb	Publish 0.1.0 · Ray	4h ago
cs1231-ts-etched.step	cs1231-ts: factory component page (tier=lcsc) · Ray	3h ago
cs1231-ts-hero.glb	cs1231-ts: hero GLB from the etched model (keeps the MPN mark) · Ray	3h ago
cs1231-ts-hero.overlay.json	Publish 0.1.0 · Ray	4h ago
cs1231-ts.glb	Publish 0.1.0 · Ray	4h ago
cs1231-ts.kicad_mod	Publish 0.1.0 · Ray	4h ago
cs1231-ts.kicad_sym	Publish 0.1.0 · Ray	4h ago
cs1231-ts.lbr	Publish 0.1.0 · Ray	4h ago
cs1231-ts.step	Publish 0.1.0 · Ray	4h ago
package.json	Publish 0.1.0 · Ray	4h ago
page.json	Set visibility: public · Ray	3h ago
README.md	Publish 0.1.0 · Ray	4h ago

CS1231-TS

CHIPSEA · Analog To Digital Converters (ADCs) · TSSOP-16

CS1231-TS from CHIPSEA, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DVDD	power_in	Digital power supply, 2.8 V to 5.5 V (absolute max 6 V).
2	DGND	power_in	Digital ground.
3	CLKIN	input	External clock input, 0.2 to 8 MHz (4.9152 MHz typical); tie low to use the internal oscillator.
4	GAIN	input	PGA gain select: GAIN=0 gives PGA=64, GAIN=1 gives PGA=128.
5	CAP1	passive	PGA amplifier output; a 0.1 uF capacitor is connected between CAP1 and CAP2.
6	CAP2	passive	PGA amplifier output; a 0.1 uF capacitor is connected between CAP1 and CAP2.
7	AINP	input	Positive analog input of the differential channel; common-mode range AGND+1.5 V to AVDD-1.5 V.
8	AINN	input	Negative analog input of the differential channel; common-mode range AGND+1.5 V to AVDD-1.5 V.
9	REFN	input	Negative reference voltage input, AGND-0.1 V to AGND+0.6 V.
10	REFP	input	Positive reference voltage input; REFP-REFN must be at least 2.5 V at 5 V supply (1.5 V at 3 V) and up to AVDD.
11	AGND	power_in	Analog ground.
12	AVDD	power_in	Analog power supply, 2.8 V to 5.5 V (absolute max 6 V).
13	SPEED	input	Output data rate select: SPEED=0 gives 10 Hz, SPEED=1 gives 80 Hz (at 4.9152 MHz clock).
14	PDWN	input	Active-low power-down control; pull low to enter power-down (below 1.6 uA), keep high in normal operation.
15	SCLK	input	SPI serial clock input; keep low after reading data since holding it high enters standby mode, with rise and fall times under 50 ns and up to 2 MHz.
16	DRDY/DOUT	output	SPI data output and data-ready flag; low indicates new data is ready, then the 24-bit result is shifted out MSB first on SCLK.

Key specifications

Parameter	Value
Manufacturer	CHIPSEA
Package	TSSOP-16
Category	Data Converters
Pins	16

CAD (KiCad official)

Symbol: CS1231-TS
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: cs1231-ts-etched.step / cs1231-ts-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs1231-ts.step / cs1231-ts.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: CHIPSEA datasheet (21 pp, sha256 6fe1c79201883667, retrieved 2026-10-22, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF