component
CS1180S
Public Made by Adomby adom
CHIPSEA Analog To Digital Converters (ADCs), SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCS1180S
CHIPSEA · Analog To Digital Converters (ADCs) · SOP-16
CS1180S from CHIPSEA, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DGND | power_in | Digital ground. |
| 2 | MCLK | input | Master clock input; the pin table gives 1~10MHz, and an external clock is applied here with XTAL left floating. |
| 3 | XTAL | output | Crystal drive pin; leave floating when an external clock is applied to MCLK, and fit 10~20pF capacitors on both MCLK and XTAL when using a crystal. |
| 4 | DGND | power_in | Digital ground. |
| 5 | REFP | input | Analog positive reference voltage input, which must not exceed the supply voltage. |
| 6 | REFN | input | Analog negative reference voltage input, which must not exceed the supply voltage. |
| 7 | AIN0 | input | Analog input, positive (AIN+). |
| 8 | AIN1 | input | Analog input, negative (AIN-). |
| 9 | AGND | power_in | Analog ground. |
| 10 | AVDD | power_in | Analog supply voltage, 2.7V~5.25V. |
| 11 | CS | input | Chip select, active low; must stay low during communication and a high level resets the SPI bus. |
| 12 | SDI | input | Serial data input. |
| 13 | SDO | tri_state | Serial data output, high-impedance when not in use so it can be tied to SDI on a bidirectional bus. |
| 14 | SCLK | input | Serial clock input with Schmitt trigger. |
| 15 | DRDY | output | Data ready indicator, active low. |
| 16 | DVDD | power_in | Digital supply voltage, 2.7~5.25V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CHIPSEA |
| Package | SOP-16 |
| Category | Data Converters |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog supply voltage (absolute max) | AVDD | -0.3 | 6 | V | AVDD to AGND | 8 | |
| Digital supply voltage (absolute max) | DVDD | -0.3 | 6 | V | DVDD to DGND | 8 | |
| DGND to AGND voltage difference | DVGND | -0.3 | 0.3 | V | DGND to AGND | 8 | |
| Input current momentary | 100 | mA | Input Current momentary | 8 | |||
| Input current continuous | 10 | mA | Input Current continuous | 8 | |||
| Digital input voltage | -0.3 | 1 | V | Max is DVDD+0.3 | 8 | ||
| Digital output voltage to DGND | -0.3 | 1 | V | Max is DVDD+0.3 | 8 | ||
| Maximum junction temperature | 150 | °C | Max. Junction Temperature | 8 | |||
| Operating temperature | -40 | 85 | °C | Operating Temperature | 8 | ||
| Storage temperature | -60 | 150 | °C | Storage Temperature | 8 | ||
| Lead soldering temperature | 300 | °C | Lead Temperature (Soldering, 10s) | 8 | |||
| Input high leakage current | IIH | 10 | uA | VI=DVDD | 8 | ||
| Input low leakage current | IIL | -10 | uA | VI=DGND | 8 | ||
| Clock frequency | fosc | 1 | 5 | MHz | 8 | ||
| Clock period | tosc | 200 | 1000 | ns | 8 | ||
| Analog supply voltage (5V table) | AVDD | 4.75 | 5.25 | V | AVDD=5V table | 10 | |
| Analog supply voltage (3V table) | AVDD | 2.7 | 3.3 | V | AVDD=3V table | 11 | |
| PGA gain range | 1 | 128 | 10 | ||||
| Power supply rejection ratio (5V) | 80 | 95 | dB | DC, AVDD=5V | 10 | ||
| Power supply rejection ratio (3V) | 75 | 90 | dB | DC, AVDD=3V | 11 | ||
| Reference input VREF, RAN=0 (5V) | VREF | 0.1 | 2.5 | 2.6 | V | RAN = 0, AVDD=5V | 10 |
| Reference input VREF, RAN=0 (3V) | VREF | 0.1 | 1.25 | 1.3 | V | RAN = 0, AVDD=3V | 11 |
| Reference input VREF, RAN=1 (3V) | VREF | 0 | 2.5 | 2.6 | V | RAN = 1, AVDD=3V | 11 |
| Reference input VREF, RAN=1 (5V) | VREF | 0 | 2.5 | V | RAN = 1, AVDD=5V; max printed as AVDD | 10 | |
| Resolution | 20 | Bits | No missing codes | 10 | |||
| Integral nonlinearity | 0.0015 | % of FS | ±0.0015, AVDD=5V and 3V | 10 | |||
| Offset error (5V) | 8 | ppm of FS | AVDD=5V | 10 | |||
| Offset error drift (5V) | 0.02 | ppm of FS/℃ | AVDD=5V | 10 | |||
| Gain error (5V) | 0.005 | % | AVDD=5V | 10 | |||
| Gain error drift (5V) | 0.5 | ppm/℃ | AVDD=5V | 10 | |||
| Offset error (3V) | 15 | ppm of FS | AVDD=3V | 11 | |||
| Offset error drift (3V) | 0.04 | ppm of FS/℃ | AVDD=3V | 11 | |||
| Gain error (3V) | 0.01 | % | AVDD=3V | 11 | |||
| Gain error drift (3V) | 1 | ppm/℃ | AVDD=3V | 11 | |||
| Input capacitance | 9 | pF | 10 | ||||
| Input leakage current | 5 | pA | Modulator off, T = 25℃ | 10 | |||
| Analog current, PGA=1, buffer off (5V) | 350 | nA | PGA = 1, Buffer off, AVDD=5V | 10 | |||
| Analog current, PGA=1, buffer on (5V) | 470 | uA | PGA = 1, Buffer on, AVDD=5V | 10 | |||
| Analog current, PGA=128, buffer off (5V) | 400 | uA | PGA = 128, Buffer off, AVDD=5V | 10 | |||
| Analog current, PGA=128, buffer on (5V) | 630 | uA | PGA = 128, Buffer on, AVDD=5V | 10 | |||
| Digital current, normal mode (5V) | 1.4 | mA | Normal mode, AVDD=5V | 10 | |||
| Analog current, PGA=1, buffer on (3V) | 450 | uA | PGA = 1, Buffer on, AVDD=3V | 11 | |||
| Analog current, PGA=128, buffer off (3V) | 350 | uA | PGA = 128, Buffer off, AVDD=3V | 11 | |||
| Analog current, PGA=128, buffer on (3V) | 630 | uA | PGA = 128, Buffer on, AVDD=3V | 11 | |||
| Digital current, normal mode (3V) | 1.1 | mA | Normal mode, AVDD=3V | 11 | |||
| SCLK period | ts | 4 | tosc periods | 13 | |||
| SCLK pulse width, high and low | tspw | 200 | ns | 13 | |||
| CS falling edge to first SCLK edge setup | tcs1 | 0 | ns | 13 | |||
| SDI data setup time | tds | 50 | ns | 13 | |||
| SDI data hold time | tdh | 50 | ns | 13 | |||
| Last SDI SCLK edge to first SDO SCLK edge | tdio | 50 | tosc periods | RDATA, RREG, WREG | 13 | ||
| CS low hold after last SCLK edge | tcs2 | 0 | ns | 13 |
CAD (KiCad official)
- Symbol:
CS1180S - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cs1180s-etched.step/cs1180s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cs1180s.step/cs1180s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CHIPSEA datasheet (30 pp, sha256
5eb0593f504c446f, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).