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CRTM030N04L

Public Made by Adom

by adom

CRMICRO MOSFETs, DFN-8-EP(5x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CRTM030N04L

CRMICRO · MOSFETs · DFN-8-EP(5x6)

CRTM030N04L from CRMICRO, in a DFN-8-EP(5x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal S1 of the N-MOSFET, tied to the other source pins; the package-limited continuous drain current is 80A at TC=25°C.
2 S passive Source terminal S2 of the N-MOSFET, tied to the other source pins; the package-limited continuous drain current is 80A at TC=25°C.
3 S passive Source terminal S3 of the N-MOSFET, tied to the other source pins; the package-limited continuous drain current is 80A at TC=25°C.
4 G input Gate terminal G4 of the N-MOSFET, with a maximum gate-source voltage of ±20V.
5 D passive Drain terminal D5 of the N-MOSFET, with a maximum drain-source voltage of 40V.
6 D passive Drain terminal D6 of the N-MOSFET, with a maximum drain-source voltage of 40V.
7 D passive Drain terminal D7 of the N-MOSFET, with a maximum drain-source voltage of 40V.
8 D passive Drain terminal D8 of the N-MOSFET, with a maximum drain-source voltage of 40V.
9 D passive Exposed drain pad on the bottom of the package, shown joined to the drain pins D5-D8 in the bottom view.

Key specifications

Parameter Value
Manufacturer CRMICRO
Package DFN-8-EP(5x6)
Category Transistors/Thyristors
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage VDS 40 V 1
Gate-source voltage VGS -20 20 V 1
Continuous drain current ID 116 A TC = 25°C (Silicon limit) 1
Continuous drain current ID 80 A TC = 25°C (Package limit) 1
Continuous drain current ID 74 A TC = 100°C (Silicon limit) 1
Pulsed drain current ID pulse 320 A TC = 25°C, tp limited by Tjmax 1
Avalanche energy, single pulse EAS 210 mJ L=0.5mH, Rg=25Ω 1
Power dissipation Ptot 61 W TC = 25°C 1
Operating junction and storage temperature Tj, Tstg -55 150 °C 1
Soldering temperature, wave soldering only allowed at leads Tsold 260 °C 1.6mm from case for 10s 1
Thermal resistance, junction to case RthJC 2.04 °C/W 2
Thermal resistance, junction to ambient RthJA 70 °C/W min. footprint 2
Drain-source breakdown voltage BVDSS 40 V VGS=0V, ID=250uA 2
Gate threshold voltage VGS(th) 1.3 2 2.7 V VDS=VGS, ID=250uA 2
Zero gate voltage drain current (Tj=25°C) IDSS 0.05 1 µA VDS=40V, VGS=0V, Tj=25°C 2
Zero gate voltage drain current (Tj=150°C) IDSS 100 µA VDS=40V, VGS=0V, Tj=150°C 2
Gate-source leakage current IGSS 10 100 nA VGS=±20V, VDS=0V 2
Drain-source on-state resistance RDS(on) 2.9 3.5 mΩ VGS=4.5V, ID=30A 2
Drain-source on-state resistance (Tj=150°C) RDS(on) 3.7 4.5 mΩ Tj=150°C 2
Body diode continuous forward current IS 80 A TC = 25°C 3
Body diode forward voltage VSD 0.9 1.3 V VGS=0V, ISD=40A 3

CAD (KiCad official)

  • Symbol: CRTM030N04L
  • Footprint: Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm
  • 3D model: DFN-8-EP(5x6) (KiCad packages3D, STEP)
  • 3D model files: crtm030n04l-etched.step / crtm030n04l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); crtm030n04l.step / crtm030n04l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CRMICRO datasheet (9 pp, sha256 c159a14a1de0be1f, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF