10 Ω Resistor 0402 - Bourns CR0402-FX-10R0GLF

@@ -23,6 +23,15 @@ CR0402-FX-10R0GLF is the 10 Ω member of Bourns’ CR series of general-purp  Design against 1/16 W at 70 °C ambient, the rating derates linearly above that and reaches zero at +155 °C (p.1, p.3), and keep continuous voltage at or below 50 V; the 100 V figure is an overload limit, not a working one. (p.1) TCR is ±100 ppm/°C across the 10 Ω-1 MΩ ±1 % band this value sits in. (p.1) At a value this low the 1 A rated current (2.5 A max overload) is the other ceiling to watch. (p.1) A 2.5× rated-voltage, 5-second overload is allowed to shift the value by up to ±(2 % + 0.1 Ω), worth knowing if a transient can land across it. (p.4) +## 3D model provenance++Bourns publishes no 3D model for the CR series, so the STEP is **AI-generated** from the Bourns CR Series datasheet+(REV. 03/21, p.2 Product Dimensions, CR0402 row) with OpenCascade: L 1.00, W 0.50, T 0.32 mm, top terminal C 0.20 mm,+bottom terminal D 0.25 mm, as a white alumina body with a black overcoat between tin-plated wrap-around terminals.+The marked STEP carries the part number from the mark planner; `CR0402-FX-10R0GLF-unetched.step` is the same model without it.+The previous model (KiCad's generic R_0402_1005Metric) is kept in `provenance/`, with the builder in+`provenance/tools/`.+ ## Footprint  Redrawn from the datasheet land pattern (the previous pads were off by up to 0.1 mm).@@ -41,6 +50,33 @@ Corners: square, as the datasheet draws them. The datasheet does not call for ro  ::adom-footprint-variants{src="/adom/cr0402-fx-10r0glf/render/footprint-variants/CR0402-FX-10R0GLF.variants.json" heading="Pad corners: this footprint (square, as drawn) and KiCad default rounding (not used)"} +### Why the pads line up flush with the chip's terminals++Seen from underneath, each pad's inner edge sits exactly on the inner edge of the chip's bottom terminal, the pad+is exactly as wide as the chip, and the copper reaches past the chip only at its two outer ends. That is the+intended fit, and it follows the land-pattern standard and the Bourns datasheet:++- **IPC-7351B solder-joint goals** for chip resistors and capacitors smaller than 0603 (1608 metric), nominal+  density: toe 0.20 mm, heel 0.00 mm, side 0.00 mm (summarised on the+  [PCB Libraries forum](https://www.pcblibraries.com/forum/topic2813.html)). The toe is the copper beyond the+  terminal's outer end, where the solder fillet forms and is inspected; heel and side are the copper inside and+  beside the terminal, and their nominal goal is zero.+- **Bourns CR Series datasheet** (REV. 03/21, p.2): CR0402 body L 1.00 +/- 0.05, W 0.50 +/- 0.05, T 0.32 +/- 0.05,+  bottom terminal D 0.25 +/- 0.10 mm; Recommended Pad Layout a (gap) 0.50 to 0.60, b (overall) 1.40 to 1.60,+  c (pad width) 0.40 to 0.60 mm.++This footprint uses a 0.50, b 1.50, c 0.50 mm, all inside Bourns' table:++| Goal | IPC-7351B nominal | This footprint | From |+|---|---|---|---|+| Toe | 0.20 mm | 0.25 mm | (b - L) / 2 = (1.50 - 1.00) / 2 |+| Heel | 0.00 mm | 0.00 mm | (L / 2 - D) - a / 2 = 0.25 - 0.25 |+| Side | 0.00 mm | 0.00 mm | (c - W) / 2 = (0.50 - 0.50) / 2 |++In the 3D viewer the part is seated at z = 0, the top of the copper. The pad outlines and the copper fill are+drawn 0.02 mm below it so they never flicker against the part, which can read as a hairline gap when you zoom in+close.+ ## Chip outline  The part's 3D outline in the standard pose (pad 1 toward the viewer), drawn from the STEP by Adom's OpenCascade service; the part number sits where the laser-etched mark is on the 3D model and reads the same way.