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CPH6341-TL-E-VB

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by adom

VBsemi Elec MOSFETs, TSOP-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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docs cph6341-tl-e-vb: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers cph6341-tl-e-vb: viewers · Ray 1mo ago
cph6341-tl-e-vb-etched.fit.json cph6341-tl-e-vb: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cph6341-tl-e-vb-etched.glb cph6341-tl-e-vb: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cph6341-tl-e-vb-etched.step cph6341-tl-e-vb: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cph6341-tl-e-vb.glb Publish 0.1.0 · Ray 1mo ago
cph6341-tl-e-vb.kicad_mod Publish 0.1.0 · Ray 1mo ago
cph6341-tl-e-vb.kicad_sym Publish 0.1.0 · Ray 1mo ago
cph6341-tl-e-vb.lbr Publish 0.1.0 · Ray 1mo ago
cph6341-tl-e-vb.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json cph6341-tl-e-vb: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md cph6341-tl-e-vb: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

CPH6341-TL-E-VB

VBsemi Elec · MOSFETs · TSOP-6

CPH6341-TL-E-VB from VBsemi Elec, in a TSOP-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D passive Drain. Pins 1, 2, 5, and 6 are internally connected to the drain of the P-channel MOSFET; tie them together for current handling and thermal spread. VDS(max) = -30 V, ID = -4.8 A at TC = 25 °C.
2 D passive Drain (internally connected to pins 1, 5, 6). Recommend tying all four drain pads to the same net on the PCB for RDS(on) and thermal performance.
3 G input Gate. Controls the P-channel MOSFET channel. VGS(th) typically between -0.5 V and -2.0 V; absolute maximum VGS = ±20 V. Gate resistance Rg ≈ 7 Ω; total gate charge Qg ≈ 5.1 nC at VGS = -4.5 V.
4 S passive Source. Single source pin (pin 4) of the P-channel MOSFET. Body diode is present from drain to source (VSD typ -0.8 V, max -1.2 V at IS = -3.3 A).
5 D passive Drain (internally connected to pins 1, 2, 6). Same net as the other drain pads.
6 D passive Drain (internally connected to pins 1, 2, 5). Same net as the other drain pads.

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package TSOP-6
Category Transistors/Thyristors
Pins 6

Ordering variants

Same part, different packaging or reel option.

  • CPH6341-TL-E-VB

CAD (KiCad official)

  • Symbol: CPH6341-TL-E-VB
  • Footprint: Package_SO:TSOP-6_1.65x3.05mm_P0.95mm
  • 3D model: TSOP-6 (KiCad packages3D, STEP)
  • 3D model files: cph6341-tl-e-vb-etched.step / cph6341-tl-e-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cph6341-tl-e-vb.step / cph6341-tl-e-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (None pp, sha256 2f35afd94b34e8b0, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF