component
CP2112-F03-GMR
Public Made by Adomby adom
SILICON LABS USB ICs, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CP2112-F03-GMR
SILICON LABS · USB ICs · QFN-24-EP(4x4)
CP2112-F03-GMR from SILICON LABS, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SDA | bidirectional | Serial Data signal for SMBus interface. |
| 2 | GND | power_in | Ground; must be tied to ground. |
| 3 | D+ | bidirectional | USB D+ data line. |
| 4 | D- | bidirectional | USB D- data line. |
| 5 | VIO | power_in | I/O supply voltage input (1.8 V to VDD). |
| 6 | VDD | power_in | Power supply voltage input, also the voltage regulator output (3.45 V on-chip regulator). |
| 7 | REGIN | power_in | 5 V regulator input; input to the on-chip voltage regulator. |
| 8 | VBUS | power_in | VBUS sense input; should be connected to the VBUS signal of a USB network. |
| 9 | /RST | bidirectional | Device reset; open-drain output of internal POR or VDD monitor, and an external source can reset the system by driving it low. |
| 10 | NC | unconnected | Should be left unconnected or tied to VIO. |
| 11 | SUSPEND | output | Logic high when the CP2112 is in the USB Suspend state. |
| 12 | GPIO.7_CLK | bidirectional | User-configurable input or output; in CLK mode outputs a clock signal with configurable frequency. |
| 13 | GPIO.6 | bidirectional | User-configurable input or output. |
| 14 | GPIO.5 | bidirectional | User-configurable input or output. |
| 15 | GPIO.4 | bidirectional | User-configurable input or output. |
| 16 | VPP | passive | Connect a 4.7 µF capacitor between this pin and ground to support ROM programming via the USB interface. |
| 17 | /SUSPEND | output | Logic low when the CP2112 is in the USB Suspend state. |
| 18 | NC | unconnected | No connect. |
| 19 | NC | unconnected | No connect. |
| 20 | GPIO.3 | bidirectional | User-configurable input or output. |
| 21 | GPIO.2 | bidirectional | User-configurable input or output. |
| 22 | GPIO.1_RXT | bidirectional | User-configurable input or output; in RXT mode it is the Receive Toggle pin, toggling to indicate SMBus transmission and high when none is in progress. |
| 23 | GPIO.0_TXT | bidirectional | User-configurable input or output; in TXT mode it is the Transmit Toggle pin, toggling to indicate SMBus transmission and high when none is in progress. |
| 24 | SCL | bidirectional | Serial Clock signal for SMBus interface. |
| 25 | GND | power_in | Center exposed pad, ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | QFN-24-EP(4x4) |
| Category | Interface ICs |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Digital Supply Voltage | VDD | 3 | 3.6 | V | 4 | ||
| Digital Port I/O Supply Voltage | VIO | 1.8 | V | 4 | |||
| Voltage on VPP during ROM programming | VPP | 5.75 | V | VIO ≥ 3.3 V | 4 | ||
| Supply Current 1 (normal operation, VREG enabled) | IDD | 15 | 16 | mA | Normal Operation; VREG Enabled | 4 | |
| Supply Current 1 (suspended, VREG enabled) | IDD | 130 | 230 | µA | Suspended; VREG Enabled | 4 | |
| Supply Current - USB Pull-up | IUSB | 200 | 228 | µA | 4 | ||
| Specified Operating Temperature Range | TA | -40 | 85 | °C | 4 | ||
| Output Low Voltage | VOL | 0.1 | V | IOL = 10 µA | 5 | ||
| Output Low Voltage | VOL | 0.4 | V | IOL = 8.5 mA | 5 | ||
| Input Low Voltage | VIL | 0.6 | V | 5 | |||
| Input Leakage Current (weak pull-up off) | ILK | 1 | µA | Weak Pull-Up Off | 5 | ||
| Input Leakage Current (weak pull-up on) | ILK | 25 | 50 | µA | Weak Pull-Up On, VIO = 0 V | 5 | |
| Maximum Input Voltage | VIN-MAX | 5.8 | V | Open drain, logic high (1) | 5 | ||
| /RST Input Low Voltage | VIL-RST | 0.6 | V | 5 | |||
| Minimum /RST Low Time to Generate a System Reset | tRSTL | 15 | µs | 5 | |||
| VDD Ramp Time | tRMP | 1 | ms | 5 | |||
| Input Voltage Range | VREGIN | 3 | 5.25 | V | 5 | ||
| Output Voltage VDD | VDD | 3.3 | 3.45 | 3.6 | V | Output Current = 1 to 100 mA | 5 |
| VBUS Detection Input Threshold | VIH-VBUS | 2.5 | V | 5 | |||
| Bias Current | IREG | 120 | µA | 5 | |||
| I2C Operating Frequency | fI2C | 0 | 702 | kHz | Standard Mode (100 kHz Class) | 7 | |
| SMBus Operating Frequency | fSMB | 401 | 702 | kHz | Standard Mode (100 kHz Class) | 7 | |
| Bus Free Time Between STOP and START Conditions | tBUF | 9.4 | µs | Standard Mode (100 kHz Class) | 7 | ||
| Hold Time After (Repeated) START Condition | tHD:STA | 4.7 | µs | Standard Mode (100 kHz Class) | 7 | ||
| Repeated START Condition Setup Time | tSU:STA | 9.4 | µs | Standard Mode (100 kHz Class) | 7 | ||
| STOP Condition Setup Time | tSU:STO | 9.4 | µs | Standard Mode (100 kHz Class) | 7 | ||
| Data Hold Time | tHD:DAT | 489 | ns | Standard Mode (100 kHz Class) | 7 | ||
| Data Setup Time | tSU:DAT | 448 | ns | Standard Mode (100 kHz Class) | 7 | ||
| Detect Clock Low Timeout | tTIMEOUT | 25 | ms | Standard Mode (100 kHz Class) | 7 | ||
| Clock Low Period | tLOW | 4.7 | µs | Standard Mode (100 kHz Class) | 7 | ||
| Clock High Period | tHIGH | 9.4 | 503 | µs | Standard Mode (100 kHz Class) | 7 | |
| I2C Operating Frequency | fI2C | 0 | 2552 | kHz | Fast Mode (400 kHz Class) | 7 | |
| SMBus Operating Frequency | fSMB | 401 | 2552 | kHz | Fast Mode (400 kHz Class) | 7 | |
| Bus Free Time Between STOP and START Conditions | tBUF | 2.6 | µs | Fast Mode (400 kHz Class) | 7 | ||
| Hold Time After (Repeated) START Condition | tHD:STA | 1.3 | µs | Fast Mode (400 kHz Class) | 7 | ||
| Repeated START Condition Setup Time | tSU:STA | 2.6 | µs | Fast Mode (400 kHz Class) | 7 | ||
| STOP Condition Setup Time | tSU:STO | 2.6 | µs | Fast Mode (400 kHz Class) | 7 | ||
| Clock Low Period | tLOW | 1.3 | µs | Fast Mode (400 kHz Class) | 7 | ||
| Clock High Period | tHIGH | 2.6 | 503 | µs | Fast Mode (400 kHz Class) | 7 | |
| Ambient Temperature Under Bias | TBIAS | -55 | 125 | °C | 8 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 8 | ||
| Voltage on /RST, SDA, SCL, or GPIO Pins with respect to GND | VGPIO | -0.3 | 5.8 | V | VIO ≥ 2.2 V | 8 | |
| Voltage on /RST, SDA, SCL, or GPIO Pins with respect to GND | VGPIO | -0.3 | V | VIO < 2.2 V | 8 | ||
| Voltage on VBUS with respect to GND | VBUS | -0.3 | 5.8 | V | VDD ≥ 3.0 V | 8 | |
| Voltage on VBUS with respect to GND | VBUS | -0.3 | V | VDD not powered | 8 | ||
| Voltage on VDD or VIO with respect to GND | VDD or VIO | -0.3 | 4.2 | V | 8 | ||
| Maximum Total Current through VDD, VIO, and GND | IDD or IIO | 500 | mA | 8 | |||
| Maximum Output Current sunk by /RST or any I/O pin | IGPIO | 100 | mA | 8 | |||
| Operating Junction Temperature | TJ | -40 | 105 | °C | 8 | ||
| Output Low Voltage | VOL | 0.6 | V | IOL = 25 mA | 5 | ||
| Capacitor on VPP for ROM programming | CPP | 4.7 | µF | 4 | |||
| TX Toggle Rate | fTX | 10 | Hz | 6 | |||
| RX Toggle Rate | fRX | 10 | Hz | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. | 12 |
CAD (KiCad official)
- Symbol:
CP2112-F03-GMR - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
cp2112-f03-gmr-etched.step/cp2112-f03-gmr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cp2112-f03-gmr.step/cp2112-f03-gmr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SILICON LABS datasheet (27 pp, sha256
674078bf07ef50fa, retrieved 2026-11-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CP2112-F03-GMR
**SILICON LABS** · USB ICs · QFN-24-EP(4x4)
CP2112-F03-GMR from SILICON LABS, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SDA | bidirectional | Serial Data signal for SMBus interface. |
| 2 | GND | power_in | Ground; must be tied to ground. |
| 3 | D+ | bidirectional | USB D+ data line. |
| 4 | D- | bidirectional | USB D- data line. |
| 5 | VIO | power_in | I/O supply voltage input (1.8 V to VDD). |
| 6 | VDD | power_in | Power supply voltage input, also the voltage regulator output (3.45 V on-chip regulator). |
| 7 | REGIN | power_in | 5 V regulator input; input to the on-chip voltage regulator. |
| 8 | VBUS | power_in | VBUS sense input; should be connected to the VBUS signal of a USB network. |
| 9 | /RST | bidirectional | Device reset; open-drain output of internal POR or VDD monitor, and an external source can reset the system by driving it low. |
| 10 | NC | unconnected | Should be left unconnected or tied to VIO. |
| 11 | SUSPEND | output | Logic high when the CP2112 is in the USB Suspend state. |
| 12 | GPIO.7_CLK | bidirectional | User-configurable input or output; in CLK mode outputs a clock signal with configurable frequency. |
| 13 | GPIO.6 | bidirectional | User-configurable input or output. |
| 14 | GPIO.5 | bidirectional | User-configurable input or output. |
| 15 | GPIO.4 | bidirectional | User-configurable input or output. |
| 16 | VPP | passive | Connect a 4.7 µF capacitor between this pin and ground to support ROM programming via the USB interface. |
| 17 | /SUSPEND | output | Logic low when the CP2112 is in the USB Suspend state. |
| 18 | NC | unconnected | No connect. |
| 19 | NC | unconnected | No connect. |
| 20 | GPIO.3 | bidirectional | User-configurable input or output. |
| 21 | GPIO.2 | bidirectional | User-configurable input or output. |
| 22 | GPIO.1_RXT | bidirectional | User-configurable input or output; in RXT mode it is the Receive Toggle pin, toggling to indicate SMBus transmission and high when none is in progress. |
| 23 | GPIO.0_TXT | bidirectional | User-configurable input or output; in TXT mode it is the Transmit Toggle pin, toggling to indicate SMBus transmission and high when none is in progress. |
| 24 | SCL | bidirectional | Serial Clock signal for SMBus interface. |
| 25 | GND | power_in | Center exposed pad, ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | QFN-24-EP(4x4) |
| Category | Interface ICs |
| Pins | 25 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Digital Supply Voltage | VDD | 3 | | 3.6 | V | | 4 |
| Digital Port I/O Supply Voltage | VIO | 1.8 | | | V | | 4 |
| Voltage on VPP during ROM programming | VPP | 5.75 | | | V | VIO ≥ 3.3 V | 4 |
| Supply Current 1 (normal operation, VREG enabled) | IDD | | 15 | 16 | mA | Normal Operation; VREG Enabled | 4 |
| Supply Current 1 (suspended, VREG enabled) | IDD | | 130 | 230 | µA | Suspended; VREG Enabled | 4 |
| Supply Current - USB Pull-up | IUSB | | 200 | 228 | µA | | 4 |
| Specified Operating Temperature Range | TA | -40 | | 85 | °C | | 4 |
| Output Low Voltage | VOL | | | 0.1 | V | IOL = 10 µA | 5 |
| Output Low Voltage | VOL | | | 0.4 | V | IOL = 8.5 mA | 5 |
| Input Low Voltage | VIL | | | 0.6 | V | | 5 |
| Input Leakage Current (weak pull-up off) | ILK | | | 1 | µA | Weak Pull-Up Off | 5 |
| Input Leakage Current (weak pull-up on) | ILK | | 25 | 50 | µA | Weak Pull-Up On, VIO = 0 V | 5 |
| Maximum Input Voltage | VIN-MAX | | | 5.8 | V | Open drain, logic high (1) | 5 |
| /RST Input Low Voltage | VIL-RST | | | 0.6 | V | | 5 |
| Minimum /RST Low Time to Generate a System Reset | tRSTL | 15 | | | µs | | 5 |
| VDD Ramp Time | tRMP | | | 1 | ms | | 5 |
| Input Voltage Range | VREGIN | 3 | | 5.25 | V | | 5 |
| Output Voltage VDD | VDD | 3.3 | 3.45 | 3.6 | V | Output Current = 1 to 100 mA | 5 |
| VBUS Detection Input Threshold | VIH-VBUS | 2.5 | | | V | | 5 |
| Bias Current | IREG | | | 120 | µA | | 5 |
| I2C Operating Frequency | fI2C | 0 | | 702 | kHz | Standard Mode (100 kHz Class) | 7 |
| SMBus Operating Frequency | fSMB | 401 | | 702 | kHz | Standard Mode (100 kHz Class) | 7 |
| Bus Free Time Between STOP and START Conditions | tBUF | 9.4 | | | µs | Standard Mode (100 kHz Class) | 7 |
| Hold Time After (Repeated) START Condition | tHD:STA | 4.7 | | | µs | Standard Mode (100 kHz Class) | 7 |
| Repeated START Condition Setup Time | tSU:STA | 9.4 | | | µs | Standard Mode (100 kHz Class) | 7 |
| STOP Condition Setup Time | tSU:STO | 9.4 | | | µs | Standard Mode (100 kHz Class) | 7 |
| Data Hold Time | tHD:DAT | 489 | | | ns | Standard Mode (100 kHz Class) | 7 |
| Data Setup Time | tSU:DAT | 448 | | | ns | Standard Mode (100 kHz Class) | 7 |
| Detect Clock Low Timeout | tTIMEOUT | 25 | | | ms | Standard Mode (100 kHz Class) | 7 |
| Clock Low Period | tLOW | 4.7 | | | µs | Standard Mode (100 kHz Class) | 7 |
| Clock High Period | tHIGH | 9.4 | | 503 | µs | Standard Mode (100 kHz Class) | 7 |
| I2C Operating Frequency | fI2C | 0 | | 2552 | kHz | Fast Mode (400 kHz Class) | 7 |
| SMBus Operating Frequency | fSMB | 401 | | 2552 | kHz | Fast Mode (400 kHz Class) | 7 |
| Bus Free Time Between STOP and START Conditions | tBUF | 2.6 | | | µs | Fast Mode (400 kHz Class) | 7 |
| Hold Time After (Repeated) START Condition | tHD:STA | 1.3 | | | µs | Fast Mode (400 kHz Class) | 7 |
| Repeated START Condition Setup Time | tSU:STA | 2.6 | | | µs | Fast Mode (400 kHz Class) | 7 |
| STOP Condition Setup Time | tSU:STO | 2.6 | | | µs | Fast Mode (400 kHz Class) | 7 |
| Clock Low Period | tLOW | 1.3 | | | µs | Fast Mode (400 kHz Class) | 7 |
| Clock High Period | tHIGH | 2.6 | | 503 | µs | Fast Mode (400 kHz Class) | 7 |
| Ambient Temperature Under Bias | TBIAS | -55 | | 125 | °C | | 8 |
| Storage Temperature | TSTG | -65 | | 150 | °C | | 8 |
| Voltage on /RST, SDA, SCL, or GPIO Pins with respect to GND | VGPIO | -0.3 | | 5.8 | V | VIO ≥ 2.2 V | 8 |
| Voltage on /RST, SDA, SCL, or GPIO Pins with respect to GND | VGPIO | -0.3 | | | V | VIO < 2.2 V | 8 |
| Voltage on VBUS with respect to GND | VBUS | -0.3 | | 5.8 | V | VDD ≥ 3.0 V | 8 |
| Voltage on VBUS with respect to GND | VBUS | -0.3 | | | V | VDD not powered | 8 |
| Voltage on VDD or VIO with respect to GND | VDD or VIO | -0.3 | | 4.2 | V | | 8 |
| Maximum Total Current through VDD, VIO, and GND | IDD or IIO | | | 500 | mA | | 8 |
| Maximum Output Current sunk by /RST or any I/O pin | IGPIO | | | 100 | mA | | 8 |
| Operating Junction Temperature | TJ | -40 | | 105 | °C | | 8 |
| Output Low Voltage | VOL | | 0.6 | | V | IOL = 25 mA | 5 |
| Capacitor on VPP for ROM programming | CPP | | 4.7 | | µF | | 4 |
| TX Toggle Rate | fTX | | 10 | | Hz | | 6 |
| RX Toggle Rate | fRX | | 10 | | Hz | | 6 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. | 12 |
## CAD (KiCad official)
- Symbol: `CP2112-F03-GMR`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `cp2112-f03-gmr-etched.step` / `cp2112-f03-gmr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cp2112-f03-gmr.step` / `cp2112-f03-gmr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [SILICON LABS datasheet](docs/cp2112-f03-gmr-datasheet.pdf) (27 pp, sha256 `674078bf07ef50fa`, retrieved 2026-11-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cp2112-f03-gmr-datasheet.pdf)