component

COS4425SR

Public Made by Adom

by adom

COSINE Gate Drive ICs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower supply chipcos4425srfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cos4425sr: viewers · Ray
cos4425sr-etched.glb Publish 0.1.0 · Ray
cos4425sr-etched.step cos4425sr: factory component page (tier=lcsc) · Ray
cos4425sr-hero.glb cos4425sr: hero GLB from the etched model (keeps the MPN mark) · Ray
cos4425sr-hero.overlay.json Publish 0.1.0 · Ray
cos4425sr.glb Publish 0.1.0 · Ray
cos4425sr.kicad_mod Publish 0.1.0 · Ray
cos4425sr.kicad_sym Publish 0.1.0 · Ray
cos4425sr.lbr Publish 0.1.0 · Ray
cos4425sr.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray

COS4425SR

COSINE · Gate Drive ICs · SOP-8

COS4425SR from COSINE, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Pin 1 is a no-connection pin on the SOP-8 package, as stated in the pin description table.
2 IN A input Input A is a high-impedance TTL/CMOS compatible input with 300mV of hysteresis that prevents output glitching on slow input edges.
3 GND power_in Ground is the device return pin and should have a low-impedance connection to the bias supply return, since high peak current flows out of it when the load discharges.
4 In B input Input B is a high-impedance TTL/CMOS compatible input with 300mV of hysteresis that prevents output glitching on slow input edges.
5 OUT B output Output B is a low-impedance CMOS push-pull output that is held LOW when its input is unbiased or floating.
6 VDD power_in VDD is the bias supply for the driver and is rated for 4.5V to 25V with respect to the Ground pin, with local ceramic bypass of 1.0μF suggested.
7 OUT A output Output A is a low-impedance CMOS push-pull output that is held LOW when its input is unbiased or floating.
8 NC unconnected Pin 8 is a no-connection pin on the SOP-8 package, as stated in the pin description table.

Key specifications

Parameter Value
Manufacturer COSINE
Package SOP-8
Category Power Supply Chip
Pins 8

CAD (KiCad official)

  • Symbol: COS4425SR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: cos4425sr-etched.step / cos4425sr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cos4425sr.step / cos4425sr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: COSINE datasheet (8 pp, sha256 eae8fe8c9cd4ca52, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF