component
COS4422SR
Public Made by Adomby adom
COSINE Gate Drivers, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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COS4422SR
COSINE · Gate Drivers · SOP-8
COS4422SR from COSINE, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Bias supply for the driver, rated 4.5V to 25V with respect to GND; bypass with local ceramic capacitors sized to the capacitive load (1.0 µF suggested). Pins 1 and 8 are duplicates and both must be connected. |
| 2 | INPUT | input | High-impedance TTL/CMOS compatible control input with 300 mV hysteresis; the output is held LOW if the input is unbiased or floating. |
| 3 | NC | unconnected | No connection. |
| 4 | GND | power_in | Device return ground that should have a low-impedance connection to the bias supply return, since high peak current flows out of the ground pin(s) when the load is discharged. Pins 4 and 5 are duplicates and both must be connected. |
| 5 | GND | power_in | Device return ground that should have a low-impedance connection to the bias supply return, since high peak current flows out of the ground pin(s) when the load is discharged. Pins 4 and 5 are duplicates and both must be connected. |
| 6 | OUTPUT | output | Low-impedance CMOS push-pull gate drive output with matched pull-up and pull-down strength; held LOW if the input is unbiased or floating. Pins 6 and 7 are duplicates and both must be connected. |
| 7 | OUTPUT | output | Low-impedance CMOS push-pull gate drive output with matched pull-up and pull-down strength; held LOW if the input is unbiased or floating. Pins 6 and 7 are duplicates and both must be connected. |
| 8 | VDD | power_in | Bias supply for the driver, rated 4.5V to 25V with respect to GND; bypass with local ceramic capacitors sized to the capacitive load (1.0 µF suggested). Pins 1 and 8 are duplicates and both must be connected. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | COSINE |
| Package | SOP-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage | Vs | 28 | V | 4 | |||
| Operating junction temperature | -40 | 125 | °C | 4 | |||
| Storage temperature | -55 | 150 | °C | 4 | |||
| DC Supply Voltage | 4.5 | 25 | V | 4 | |||
| Operating ambient temperature | -40 | 125 | °C | 4 | |||
| Operating Voltage Range | VDD | 4.5 | 25 | V | 5 | ||
| Input Signal High Threshold | VIH | 1.6 | V | 5 | |||
| Input Signal Low Threshold | VIL | 0.7 | V | 5 | |||
| Low Output Voltage | VOL | 0.025 | V | DC Test | 5 | ||
| Input Signal High Current (non-inverting input) | IIH | 88 | 125 | µA | Non-inverting Input Current, VINX=18V | 5 | |
| Peak Output Current | IPK | 9 | A | 10V≤ VDD ≤18V | 5 | ||
| Under-Voltage Lockout ON Threshold | 3.7 | 4.1 | V | 5 | |||
| Under-Voltage Lockout Hysteresis | 0.5 | V | 5 | ||||
| Input Signal Hysteresis | VHYS | 0.3 | V | 5 | |||
| Input Signal High Current (non-inverting input, low-level input) | IIL | 0.01 | µA | Non-inverting Input Current, VINX=0V | 5 | ||
| Pull-Up Resistance | ROH | 0.83 | Ω | Source Current = 10mA | 5 | ||
| Pull-Down Resistance | ROL | 0.5 | Ω | Sink Current = -10mA | 5 | ||
| Power Supply Current | ICC | 0.85 | mA | VIN=3V | 5 | ||
| Power Supply Current | ICC | 0.65 | mA | VIN=0V | 5 | ||
| Rise Time | tR | 35 | ns | CL =10,000 pF, See Figure 3 | 5 | ||
| Fall Time | tF | 36 | ns | CL =10,000 pF, See Figure 3 | 5 | ||
| Turn-On Delay Time (COS4422) | tD1 | 60 | ns | COS4422, CL =10,000 pF | 6 | ||
| Turn-Off Delay Time (COS4422) | tD2 | 63 | ns | COS4422, CL =10,000 pF | 6 | ||
| Thermal Shutdown Threshold | 150 | °C | 6 | ||||
| Thermal Shutdown Threshold Hysteresis | 25 | °C | 6 | ||||
| Package Thermal Resistance (SOP8) | 155 | °C/W | SOP8 package | 4 |
CAD (KiCad official)
- Symbol:
COS4422SR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
cos4422sr-etched.step/cos4422sr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cos4422sr.step/cos4422sr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: COSINE datasheet (7 pp, sha256
f341a267c5f4756b, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# COS4422SR
**COSINE** · Gate Drivers · SOP-8
COS4422SR from COSINE, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Bias supply for the driver, rated 4.5V to 25V with respect to GND; bypass with local ceramic capacitors sized to the capacitive load (1.0 µF suggested). Pins 1 and 8 are duplicates and both must be connected. |
| 2 | INPUT | input | High-impedance TTL/CMOS compatible control input with 300 mV hysteresis; the output is held LOW if the input is unbiased or floating. |
| 3 | NC | unconnected | No connection. |
| 4 | GND | power_in | Device return ground that should have a low-impedance connection to the bias supply return, since high peak current flows out of the ground pin(s) when the load is discharged. Pins 4 and 5 are duplicates and both must be connected. |
| 5 | GND | power_in | Device return ground that should have a low-impedance connection to the bias supply return, since high peak current flows out of the ground pin(s) when the load is discharged. Pins 4 and 5 are duplicates and both must be connected. |
| 6 | OUTPUT | output | Low-impedance CMOS push-pull gate drive output with matched pull-up and pull-down strength; held LOW if the input is unbiased or floating. Pins 6 and 7 are duplicates and both must be connected. |
| 7 | OUTPUT | output | Low-impedance CMOS push-pull gate drive output with matched pull-up and pull-down strength; held LOW if the input is unbiased or floating. Pins 6 and 7 are duplicates and both must be connected. |
| 8 | VDD | power_in | Bias supply for the driver, rated 4.5V to 25V with respect to GND; bypass with local ceramic capacitors sized to the capacitive load (1.0 µF suggested). Pins 1 and 8 are duplicates and both must be connected. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | COSINE |
| Package | SOP-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage | Vs | | | 28 | V | | 4 |
| Operating junction temperature | | -40 | | 125 | °C | | 4 |
| Storage temperature | | -55 | | 150 | °C | | 4 |
| DC Supply Voltage | | 4.5 | | 25 | V | | 4 |
| Operating ambient temperature | | -40 | | 125 | °C | | 4 |
| Operating Voltage Range | VDD | 4.5 | | 25 | V | | 5 |
| Input Signal High Threshold | VIH | 1.6 | | | V | | 5 |
| Input Signal Low Threshold | VIL | | | 0.7 | V | | 5 |
| Low Output Voltage | VOL | | | 0.025 | V | DC Test | 5 |
| Input Signal High Current (non-inverting input) | IIH | | 88 | 125 | µA | Non-inverting Input Current, VINX=18V | 5 |
| Peak Output Current | IPK | | 9 | | A | 10V≤ VDD ≤18V | 5 |
| Under-Voltage Lockout ON Threshold | | 3.7 | | 4.1 | V | | 5 |
| Under-Voltage Lockout Hysteresis | | | 0.5 | | V | | 5 |
| Input Signal Hysteresis | VHYS | | 0.3 | | V | | 5 |
| Input Signal High Current (non-inverting input, low-level input) | IIL | | 0.01 | | µA | Non-inverting Input Current, VINX=0V | 5 |
| Pull-Up Resistance | ROH | | 0.83 | | Ω | Source Current = 10mA | 5 |
| Pull-Down Resistance | ROL | | 0.5 | | Ω | Sink Current = -10mA | 5 |
| Power Supply Current | ICC | | 0.85 | | mA | VIN=3V | 5 |
| Power Supply Current | ICC | | 0.65 | | mA | VIN=0V | 5 |
| Rise Time | tR | | 35 | | ns | CL =10,000 pF, See Figure 3 | 5 |
| Fall Time | tF | | 36 | | ns | CL =10,000 pF, See Figure 3 | 5 |
| Turn-On Delay Time (COS4422) | tD1 | | 60 | | ns | COS4422, CL =10,000 pF | 6 |
| Turn-Off Delay Time (COS4422) | tD2 | | 63 | | ns | COS4422, CL =10,000 pF | 6 |
| Thermal Shutdown Threshold | | | 150 | | °C | | 6 |
| Thermal Shutdown Threshold Hysteresis | | | 25 | | °C | | 6 |
| Package Thermal Resistance (SOP8) | | | 155 | | °C/W | SOP8 package | 4 |
## CAD (KiCad official)
- Symbol: `COS4422SR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `cos4422sr-etched.step` / `cos4422sr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cos4422sr.step` / `cos4422sr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [COSINE datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590411129320075264) (7 pp, sha256 `f341a267c5f4756b`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cos4422sr-datasheet.pdf)