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COS3842BD

Public Made by Adom

by adom

COSINE AC-DC Controllers And Regulators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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COS3842BD

COSINE · AC-DC Controllers And Regulators · SOP-8

COS3842BD from COSINE, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COMP output Output of the error amplifier for compensation; external compensation components connect here, and forcing COMP to ground lets the user command zero duty cycle.
2 VFB input Inverting input to the error amplifier, normally connected to the switching power supply output through a resistor divider, with a recommended input voltage of up to 2.5 V.
3 ISENSE input Input carrying a voltage proportional to inductor current that the PWM uses to terminate output switch conduction, with a recommended input voltage of up to 1 V.
4 RT/CT bidirectional Oscillator timing pin where resistor RT connects to VREF and capacitor CT connects to ground, setting oscillator frequency and maximum output duty cycle; operation up to 1 MHz is possible.
5 GROUND power_in Ground return pin functioning as both power ground and analog ground; timing and bypass capacitors should be connected close to this pin in a single-point ground.
6 OUTPUT output Output of the on-chip totem-pole drive stage that directly drives a power MOSFET gate, sourcing and sinking peak currents up to 1 A and held low when VCC is below the turn-on threshold.
7 VCC power_in Power supply pin for the control IC, rated 30 V maximum with a 7.6 V minimum supply voltage, to be bypassed with a 0.1 µF ceramic low-ESL capacitor and a bulk capacitor at least 10 times the main MOSFET gate capacitance.
8 VREF power_out 5 V reference output trimmed to 1% (4.95 V to 5.05 V), providing charging current for CT through RT, to be bypassed with a 0.1 µF ceramic low-ESL capacitor; reference load current is 0 to 20 mA.

Key specifications

Parameter Value
Manufacturer COSINE
Package SOP-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC 30 V 4
Analog Inputs VFB, ISENSE -0.3 6 V 4
Output Current, Source or Sink IO -1 1 A 4
Error Amplifier Output Sink Current ICOMP 10 mA 4
Operating Junction Temperature TJ -40 125 °C 4
Storage Temperature TS -55 150 °C 4
Lead Temperature (soldering 10s) TL 300 °C soldering 10s 4
Vcc Supply Voltage VCC 30 V 5
VFB Input Voltage VFB 2.5 V 5
ISENSE Input Voltage 1 V 5
Sink/Source Load Current (average) 200 mA 5
Reference Load Current 0 20 mA 5
Oscillator Frequency Range 100 500 kHz 5
Operating Junction Temperature -40 125 °C 5
Supply Voltage VCC 7.6 30 V 5
Operating Supply Current IS 12 17 mA VFB = VISENSE = 0 V 5
Start-up Current 0.1 0.3 mA 5
Output Voltage VREF 4.95 5 5.05 V 5
Line Regulation ΔVREF 10 20 mV VIN = 8 V to 30 V 5
Load Regulation ΔVREF 20 50 mV IL = 0 to 20 mA 5
Temp. Stability ΔVREF 20 50 mV Over operating range 5
Total Output Variation VREF 4.9 5.1 V Line, Load, and Temperature 5
Short Circuit Output Current ISC 30 100 180 mA VREF=0 5
Frequency fOSC 47 52 57 kHz RT = 10 kΩ, CT = 3.3 μF 5
Voltage Stability Δf/ΔVIN 0.2 1 % VIN = 12 V to 25 V 5
Input Voltage VFB 2.42 2.5 2.58 V 6
Input Bias Current IB 0.1 2 μA 6
Open Loop Voltage Gain GVOL 65 90 dB 2 ≤VCOMP ≤ 4 V 6
Gain-Bandwidth Product GBP 0.7 1 MHz AV = 0 dB 6
Power Supply Rejection Ratio PSRR1 60 70 dB VIN= 12V to 25V 6
COMP Sink Current ISK 2 12 mA VFB = 2.7 V, VCOMP=1.1V 6
COMP Source Current ISRC -0.5 -1 mA VFB = 2.3 V, VCOMP=5V 6
Low-level Output Voltage VOL 0.8 1.1 V VFB = 2.7 V; RL = 15-kΩ COMP to VREF 6
High-level Output Voltage VOH 5 6.2 V VFB = 2.3 V; RL = 15-kΩ COMP to Ground 6
Gain GCOMP 2.85 3 3.15 V/V G = ΔVCOMP/ΔVISENSE, 0 V ≤ VISENSE ≤ 0.8 V 6
Maximum Input Signal VISENSE 0.9 1 1.1 V 6
Input Bias Current IISENSE -2 -10 μA 6
Delay to Output tDLY 150 300 ns VISENSE stepped from 0 to 2 V 6
Low-level Output Voltage VOL I 0.2 0.4 V ISINK = 20 mA 6
Low-level Output Voltage VOL II 1.6 2.2 V ISINK = 200 mA 6
High-level Output Voltage VOH I 18 19 V ISOURCE = 20 mA 6
High-level Output Voltage VOH II 17 18 V ISOURCE = 200 mA 6
Rise Time tR 50 150 ns CL=1nF 6
Fall Time tF 50 150 ns CL=1nF 6
UVLO Enable Threshold UVLON 14.5 16 17.5 V COS3842/3844 7
UVLO Off Threshold UVLOFF 8.5 10 11.5 V COS3842/3844 7
Maximum Duty Cycle DMAX 94 96 100 % COS3842/3843 7
Package Thermal Resistance, RθJA (Junction-to-ambient) RθJA 150 °C/W SOP8 package 4

CAD (KiCad official)

  • Symbol: COS3842BD
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: cos3842bd-etched.step / cos3842bd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cos3842bd.step / cos3842bd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: COSINE datasheet (10 pp, sha256 e96e06bb1fc3da6b, retrieved 2026-10-14, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF