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Contents

README

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CMSA75N68

Cmos · MOSFETs · DFN-8(5x6)

CMSA75N68 from Cmos, in a DFN-8(5x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source of the N-channel MOSFET, with continuous drain current rated 50 A at TC=25°C.
2 S passive Source of the N-channel MOSFET, tied with the other source pins in the DFN-8 5x6 pin configuration.
3 S passive Source of the N-channel MOSFET, tied with the other source pins in the DFN-8 5x6 pin configuration.
4 G input Gate of the N-channel MOSFET, with a gate-source voltage rating of ±20 V and a threshold of 2.0 to 4.0 V.
5 D passive Drain of the N-channel MOSFET, with a drain-source voltage rating of 68 V.
6 D passive Drain of the N-channel MOSFET, tied with the other drain pins in the DFN-8 5x6 pin configuration.
7 D passive Drain of the N-channel MOSFET, tied with the other drain pins in the DFN-8 5x6 pin configuration.
8 D passive Drain of the N-channel MOSFET, with a pulsed drain current rating of 200 A.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cmos
Package DFN-8(5x6)
Category Triode/MOS Tube/Transistor
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS 68 V 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current ID 50 A TC=25℃ 1
Pulsed Drain Current IDM 200 A 1
Total Power Dissipation PD 45 W TC=25℃ 1
Storage Temperature Range TSTG -55 150 ℃ 1
Operating Junction Temperature Range TJ -55 150 ℃ 1
Single Pulse Avalanche Energy EAS 110 mJ VDD=30V, VGS=10V, L=0.5mH, IAS=21A 1
Thermal Resistance Junction-to-Ambient RθJA 42 ℃/W 1
Thermal Resistance Junction-Case RθJC 2.8 ℃/W 1
Drain-Source Breakdown Voltage BVDSS 68 V VGS=0V, ID=250uA 2
Static Drain-Source On-Resistance RDS(ON) 9 mΩ VGS=10V, ID=20A 2
Gate Threshold Voltage VGS(th) 2 4 V VGS=VDS, ID=250μA 2
Drain-Source Leakage Current IDSS 1 uA VDS=68V, VGS=0V 2
Gate-Source Leakage Current IGSS -100 100 nA VGS ±20V, VDS=0V 2
Continuous Source Current IS 50 A VG=VD=0V, Force Current 2
Pulsed Source Current ISM 200 A VG=VD=0V, Force Current 2
Diode Forward Voltage VSD 0.88 1.2 V VGS=0V, IS=20A, TJ=25℃ 2
Total Gate Charge Qg 70 nC VDS=54V, VGS=10V, ID=30A 2
Turn-On Delay Time Td(on) 22 ns VDS=34V, VGS=10V, RGEN=4.7Ω 2
Turn-Off Delay Time Td(off) 56 ns VDS=34V, VGS=10V, RGEN=4.7Ω 2
Fall Time Tf 25 ns VDS=34V, VGS=10V, RGEN=4.7Ω 2
Input Capacitance Ciss 3500 pF VDS=30V, VGS=0V, f=1MHz 2
Output Capacitance Coss 250 pF VDS=30V, VGS=0V, f=1MHz 2
Reverse Transfer Capacitance Crss 200 pF VDS=30V, VGS=0V, f=1MHz 2
Reverse Recovery Time trr 34 ns di/dt=100A/μs, VGS=0V, IS=30A 2
Reverse Recovery Charge Qrr 45 nC di/dt=100A/μs, VGS=0V, IS=30A 2

CAD (KiCad official)

  • Symbol: CMSA75N68
  • Footprint: Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm
  • 3D model: DFN-8(5x6) (KiCad packages3D, STEP)
  • 3D model files: cmsa75n68-etched.step / cmsa75n68-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cmsa75n68.step / cmsa75n68.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cmos datasheet (4 pp, sha256 33a8d548edd6837d, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF