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CM6111-DFNTA

Public Made by Adom

by adom

CIMO Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CM6111-DFNTA

CIMO · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-10(3x3)

CM6111-DFNTA from CIMO, in a DFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Regulator supply input (pins 1 and 2 tied together) requiring a 4.7μF bypass capacitor, with more input capacitance for large load transients.
2 IN power_in Regulator supply input (pins 1 and 2 tied together) requiring a 4.7μF bypass capacitor, with more input capacitance for large load transients.
3 EN/UV input Enable/undervoltage lockout: low puts the part in shutdown with quiescent current below 1μA, turn-on threshold is 1.24V rising with 80mV hysteresis, and it must not be left floating (tie to IN if unused).
4 PG output Open-drain power-good output that is pulled low when PGFB is below 300mV and may be left floating if unused.
5 ILIM passive Current-limit programming pin where a resistor to GND sets the limit with a typical scale factor of 120mA•kΩ, or connect to GND if programmable limit is not needed.
6 PGFB input Power-good feedback input with a 300mV threshold (PG goes high above 300mV) that also enables fast-start; connect to IN if PG and fast-start are not used.
7 SET passive Output voltage setting pin sourcing 100μA through an external resistor to GND (VSET = ISET×RSET, 1.7V~15V output range), where a capacitor to GND improves noise, PSRR and transient response but increases start-up time.
8 GND power_in Ground.
9 OUTS input Output sense pin, Kelvin-connected to the output capacitor and load for best regulation.
10 OUT power_out Voltage output requiring a minimum 4.7μF output capacitor with ESR below 50mΩ and ESL below 2nH for stability.
11 EPAD power_in Exposed pad, connected directly to GND to ensure electrical and thermal performance.

Key specifications

Parameter Value
Manufacturer CIMO
Package DFN-10(3x3)
Category Power Management (PMIC)
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
SET pin current ISET 98 100 102 µA 2.6V < VIN < 20V, 1.7V < VOUT < 15V, 1mA < IL < 200mA 7
Output offset voltage VOS -2 4 mV 2.6V < VIN < 20V, 1.7V < VOUT < 15V, 1mA < IL < 200mA 7
Line regulation ΔVOS ΔVOS -3 1.3 3 µV/V VIN = 2.6V~20V, VOUT = 1.7V, IL = 1mA 7
Line regulation ΔISET ΔISET -6 2.1 6 nA/V VIN = 2.6V~20V, VOUT = 1.7V, IL = 1mA 7
Load regulation ΔVOS ΔVOS 1.5 3 mV IL = 1mA~200mA, VIN = 2.6V, VOUT = 1.7V 7
ISET variation with VSET ΔISET 200 400 nA VIN = 20V, VSET = 1.7V~15V, IL = 1mA 7
VOS variation with VSET ΔVOS 0.11 0.6 mV VIN = 20V, VSET = 1.7V~15V, IL = 1mA 7
Dropout voltage 320 mV IL = 1mA, TA = 25°C 7
Dropout voltage 325 mV IL = 50mA, TA = 25°C 7
Dropout voltage 330 mV IL = 150mA, TA = 25°C 7
Dropout voltage 335 mV IL = 200mA, TA = 25°C 7
GND pin current 2.7 3.8 mA IL = 10µA, VIN = VOUT + 1V 7
GND pin current 4.1 5 mA IL = 50mA, VIN = VOUT + 1V 7
GND pin current 5 5.9 mA IL = 100mA, VIN = VOUT + 1V 7
GND pin current 6.9 7.8 mA IL = 200mA, VIN = VOUT + 1V 7
EN/UV threshold voltage 1.17 1.24 1.3 V EN/UV trip point rising (turn-on), VIN = 2.6V 8
EN/UV hysteresis 60 80 112 mV EN/UV trip point hysteresis, VIN = 2.6V, TA = 25°C 8
Shutdown quiescent current 15.7 µA VIN = 6V 8
Shutdown quiescent current 1 µA VIN = 6V, TA = 25°C 8
PG output low voltage 30 36 mV IPG = 100µA 9
PG leakage current 1 µA VPG = 20V 9
PGFB pin current 1 nA VIN = 2.6V, VPGFB = 300mV, TA = 25°C 9
Minimum IN pin voltage (VIN UVLO rising) 2.1 V IL = 200mA 7
VIN UVLO hysteresis 60 mV 7
Fast-start SET pin current 2 mA VIN = 2.8V, VPGFB = 289mV, VSET = 1.7V, TA=25°C 7
Internal current limit 300 mA VIN = 2.6V, VOUT = 0V, TA = 25°C 8
Programmable current limit scale factor 120 mA•kΩ 2.6V < VIN < 20V, TA = 25°C 8
PGFB threshold voltage 300 mV 8
PGFB hysteresis voltage 15 mV 9
Thermal shutdown TJ 170 °C TJ rising 9
Output RMS noise 0.8 µVrms 1.7V ≤ VOUT ≤ 15V, IL = 200mA, 10Hz~100kHz, COUT = 4.7µF, CSET = 4.7µF, TA = 25°C 8
Operating temperature -40 125 °C 6
Storage temperature -65 150 °C 6
Junction temperature 150 °C 6
Lead-free soldering temperature 260 °C 6
Tin-lead soldering temperature 235 °C 6
IN, EN/UV, PG, PGFB voltage -0.3 22 V 6
ILIM voltage -0.3 1 V 6
SET, OUTS, OUT voltage -0.3 16 V 6
SET to OUT/OUTS voltage -1.2 1.2 V 6
ESD HBM 2000 V 6
ESD CDM 2000 V 6
Thermal resistance junction-to-ambient θJA 41.4 °C/W 6
Thermal resistance junction-to-board θJB 15.8 °C/W 6

CAD (KiCad official)

  • Symbol: CM6111-DFNTA
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: DFN-10(3x3) (KiCad packages3D, STEP)
  • 3D model files: cm6111-dfnta-etched.step / cm6111-dfnta-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cm6111-dfnta.step / cm6111-dfnta.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CIMO datasheet (18 pp, sha256 208fe00cdab5c92f, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF