Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Download PDF

Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

CM2268-QFPTR

CIMO · Analog To Digital Converters (ADC) · LQFP-64(10x10)

CM2268-QFPTR from CIMO, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVCC	power_in	Analog supply voltage, 4.75V to 5.25V, decoupled to AGND with parallel 100nF and 10µF capacitors.
2	AGND	power_in	Analog ground, the reference point for all analog circuitry, analog inputs and external reference; all 6 AGND pins connect to the system AGND plane.
3	OS0	input	Oversampling mode pin selecting the oversampling ratio or enabling software mode (all OSx high).
4	OS1	input	Oversampling mode pin selecting the oversampling ratio or enabling software mode (all OSx high).
5	OS2	input	Oversampling mode pin selecting the oversampling ratio or enabling software mode (all OSx high).
6	PAR/SER_SEL	input	Parallel/serial interface select: logic low selects the parallel interface, logic high selects the serial interface.
7	STBY	input	Active-low standby input which, together with RANGE, selects standby or shutdown low-power mode.
8	RANGE	input	Analog input range select in hardware mode (high ±10V, low ±5V single-ended) and, with STBY low, selects standby versus shutdown mode.
9	CONVST	input	Conversion start: a low-to-high transition simultaneously samples all 8 analog inputs; can be configured as external oversampling clock in software mode.
10	WR	input	Active-low parallel write control for register writes in software mode; no function in hardware mode.
11	RESET	input	Reset input: logic high resets the device, interrupts conversions in progress and resets the output registers to all 0s.
12	RD/SCLK	input	Parallel read control input (RD) in parallel mode, serial clock input (SCLK) in serial mode.
13	CS	input	Active-low chip select for ADC data reads and register read/write in serial and parallel interfaces.
14	BUSY	output	Conversion-in-progress indicator that goes high after CONVST rises and stays high until all channel conversions complete; the falling edge latches data into the output registers.
15	FRSTDATA	tri_state	Indicates that channel V1 data is being read on the parallel or serial interface; tri-state when CS is high.
16	DB0	bidirectional	Parallel data bit DB0 in parallel mode; must be connected to AGND in serial mode.
17	DB1	bidirectional	Parallel data bit DB1 in parallel mode; must be connected to AGND in serial mode.
18	DB2	bidirectional	Parallel data bit DB2 in parallel mode; must be connected to AGND in serial mode.
19	DB3/DOUTE	bidirectional	Tri-state parallel data pin DB3 in parallel mode, serial output DOUTE in serial mode.
20	DB4/DOUTF	bidirectional	Tri-state parallel data pin DB4 in parallel mode, serial output DOUTF in serial mode.
21	DB5/DOUTG	bidirectional	Tri-state parallel data pin DB5 in parallel mode, serial output DOUTG in serial mode.
22	DB6/DOUTH	bidirectional	Tri-state parallel data pin DB6 in parallel mode, serial output DOUTH in serial mode.
23	VDRIVE	power_in	Logic supply, 1.71V to 5.25V, setting the logic interface voltage; should match the controller (DSP or FPGA) interface supply.
24	DB7/DOUTA	bidirectional	Tri-state parallel data pin DB7 in parallel mode, serial output DOUTA in serial mode.
25	DB8/DOUTB	bidirectional	Tri-state parallel data pin DB8 in parallel mode, serial output DOUTB in serial mode.
26	AGND	power_in	Analog ground; all analog input and external reference signals reference this pin, and all 6 AGND pins connect to the system AGND plane.
27	DB9/DOUTC	bidirectional	Tri-state parallel data pin DB9 in parallel mode, serial output DOUTC in serial mode.
28	DB10/DOUTD	bidirectional	Tri-state parallel data pin DB10 in parallel mode, serial output DOUTD in serial mode.
29	DB11/SDI	bidirectional	Tri-state parallel data pin DB11 in parallel mode, serial data pin SDI in serial mode.
30	DB12	bidirectional	Tri-state parallel data pin DB12 in parallel mode; connect to AGND in serial mode.
31	DB13	bidirectional	Tri-state parallel data pin DB13 in parallel mode; connect to AGND in serial mode.
32	DB14	bidirectional	Tri-state parallel data pin DB14 in parallel mode; connect to AGND in serial mode.
33	DB15	bidirectional	Tri-state parallel data pin DB15 in parallel mode; connect to AGND in serial mode.
34	REF_SELECT	input	Reference select: logic high enables the internal reference, logic low disables it and requires an external reference on REFIN/REFOUT.
35	AGND	power_in	Analog ground; all analog input and external reference signals reference this pin, and all 6 AGND pins connect to the system AGND plane.
36	REGCAP	power_out	Internal regulator output, about 1.9V, decoupled to AGND with a 1µF capacitor.
37	AVCC	power_in	Analog supply voltage, decoupled to AGND with parallel 100nF and 10µF capacitors.
38	AVCC	power_in	Analog supply voltage, decoupled to AGND with parallel 100nF and 10µF capacitors.
39	REGCAP	power_out	Internal regulator output, about 1.9V, decoupled to AGND with a 1µF capacitor.
40	AGND	power_in	Analog ground; all analog input and external reference signals reference this pin, and all 6 AGND pins connect to the system AGND plane.
41	AGND	power_in	Analog ground; all analog input and external reference signals reference this pin, and all 6 AGND pins connect to the system AGND plane.
42	REFIN/REFOUT	bidirectional	Reference input/output: provides the 2.5V internal reference when REF_SELECT is high, or takes a 2.5V external reference when low; needs a 100nF capacitor to REFGND.
43	REFGND	power_in	Reference ground pin, to be connected to AGND.
44	REFCAPA	passive	Reference buffer output, typically 4V; tie to REFCAPB and decouple to AGND with a low-ESR 10µF ceramic capacitor.
45	REFCAPB	passive	Reference buffer output, typically 4V; tie to REFCAPA and decouple to AGND with a low-ESR 10µF ceramic capacitor.
46	REFGND	power_in	Reference ground pin, to be connected to AGND.
47	AGND	power_in	Analog ground; all analog input and external reference signals reference this pin, and all 6 AGND pins connect to the system AGND plane.
48	AVCC	power_in	Analog supply voltage, decoupled to AGND with parallel 100nF and 10µF capacitors.
49	V1+	input	Channel 1 positive analog input.
50	V1-	input	Channel 1 negative analog input.
51	V2+	input	Channel 2 positive analog input.
52	V2-	input	Channel 2 negative analog input.
53	V3+	input	Channel 3 positive analog input.
54	V3-	input	Channel 3 negative analog input.
55	V4+	input	Channel 4 positive analog input.
56	V4-	input	Channel 4 negative analog input.
57	V5+	input	Channel 5 positive analog input.
58	V5-	input	Channel 5 negative analog input.
59	V6+	input	Channel 6 positive analog input.
60	V6-	input	Channel 6 negative analog input.
61	V7+	input	Channel 7 positive analog input.
62	V7-	input	Channel 7 negative analog input.
63	V8+	input	Channel 8 positive analog input.
64	V8-	input	Channel 8 negative analog input.

Key specifications

Parameter	Value
Manufacturer	CIMO
Package	LQFP-64(10x10)
Category	Data Acquisition
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
AVCC to AGND	AVCC	-0.3		6.5	V		8
VDRIVE to AGND	VDRIVE	-0.3			V	max AVCC + 0.3 V	8
Analog input voltage to AGND		-19.5		19.5	V		8
Digital input voltage to AGND		-0.3			V	max VDRIVE + 0.3 V	8
Digital output voltage to AGND		-0.3			V	max VDRIVE + 0.3 V	8
REFIN to AGND		-0.3			V	max AVCC + 0.3 V	8
Input current		-10		10	mA	any pin except supply pins	8
Operating temperature		-40		125	°C		8
Storage temperature		-65		150	°C		8
Junction temperature				150	°C		8
ESD HBM, all pins except analog inputs				2000	V		8
ESD HBM, analog input pins only				7000	V		8
ESD CDM				750	V		8
Analog supply voltage	AVCC	4.75		5.25	V		12
Logic supply voltage	VDRIVE	1.71		5.25	V		12
AVCC current, static mode	IAVCC		16.5	18	mA		12
AVCC current, standby mode	IAVCC		5	6	mA		12
AVCC current, shutdown mode	IAVCC		0.1	5	μA		12
Power, static mode			82.5	94.5	mW		12
Power, standby mode			25	31.5	mW		12
Power, shutdown mode			0.5	26	μW		12
External reference input voltage		2.495	2.5	2.505	V	external reference	12
Internal reference output voltage		2.4975	2.5	2.5025	V	internal reference, TA = 25℃	12
Reference temperature coefficient				7	ppm/℃	printed ±7	12
Input resistance	RIN		1		MΩ		12
Input impedance drift			27	32	ppm/℃		12
Resolution		16			Bits	no missing codes	11
DNL	DNL		0.5	0.9	LSB	printed ±	11
INL	INL		0.3	2	LSB	printed ±	11
tCYCLE	tCYCLE	1			μs	1/max throughput	13

CAD (KiCad official)

Symbol: CM2268-QFPTR
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: cm2268-qfptr-etched.step / cm2268-qfptr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cm2268-qfptr.step / cm2268-qfptr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: CIMO datasheet (55 pp, sha256 1d91cb279ed8f83c, retrieved 2026-10-23, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF