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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

CM2249-QFPTR

CIMO · Analog To Digital Converters (ADC) · LQFP-80(14x14)

CM2249-QFPTR from CIMO, in a LQFP-80(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	V4BGND	power_in	Analog input ground return for channel 4 input V4B (ADC B).
2	V4B	passive	Analog input for channel 4 on ADC B; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
3	V5BGND	power_in	Analog input ground return for channel 5 input V5B (ADC B).
4	V5B	passive	Analog input for channel 5 on ADC B; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
5	AGND	power_in	Analog power ground.
6	VCC	power_in	Analog supply 4.75 V to 5.25 V for the front-end amplifiers and ADC core, decoupled to AGND with 0.1 µF in parallel with 10 µF.
7	V6B	passive	Analog input for channel 6 on ADC B; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
8	V6BGND	power_in	Analog input ground return for channel 6 input V6B (ADC B).
9	V7B	passive	Analog input for channel 7 on ADC B; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
10	V7BGND	power_in	Analog input ground return for channel 7 input V7B (ADC B).
11	V7AGND	power_in	Analog input ground return for channel 7 input V7A (ADC A).
12	V7A	passive	Analog input for channel 7 on ADC A; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
13	V6AGND	power_in	Analog input ground return for channel 6 input V6A (ADC A).
14	V6A	passive	Analog input for channel 6 on ADC A; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
15	VCC	power_in	Analog supply 4.75 V to 5.25 V for the front-end amplifiers and ADC core, decoupled to AGND with 0.1 µF in parallel with 10 µF.
16	AGND	power_in	Analog power ground.
17	V5A	passive	Analog input for channel 5 on ADC A; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
18	V5AGND	power_in	Analog input ground return for channel 5 input V5A (ADC A).
19	V4A	passive	Analog input for channel 4 on ADC A; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
20	V4AGND	power_in	Analog input ground return for channel 4 input V4A (ADC A).
21	V3AGND	power_in	Analog input ground return for channel 3 input V3A (ADC A).
22	V3A	passive	Analog input for channel 3 on ADC A; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
23	V2AGND	power_in	Analog input ground return for channel 2 input V2A (ADC A).
24	V2A	passive	Analog input for channel 2 on ADC A; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
25	V1AGND	power_in	Analog input ground return for channel 1 input V1A (ADC A).
26	V1A	passive	Analog input for channel 1 on ADC A; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
27	V0AGND	power_in	Analog input ground return for channel 0 input V0A (ADC A).
28	V0A	passive	Analog input for channel 0 on ADC A; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
29	AGND	power_in	Analog power ground.
30	VCC	power_in	Analog supply 4.75 V to 5.25 V for the front-end amplifiers and ADC core, decoupled to AGND with 0.1 µF in parallel with 10 µF.
31	REFCAP	passive	Reference buffer output, typically 4 V; connect to AGND with a 10 µF low-ESR ceramic capacitor placed as close as possible to the pin.
32	REFGND	power_in	Reference ground; must be connected to AGND.
33	REFINOUT	passive	Reference input/output: provides the 2.5 V internal reference when REFSEL is high, or accepts an external 2.5 V reference when REFSEL is low; requires a 10 µF X5R capacitor to REFINOUTGND.
34	REFINOUTGND	power_in	Ground for the REFINOUT reference pin.
35	REFSEL	input	Selects internal (logic high, reference enabled) or external (logic low, internal reference disabled) 2.5 V reference; latched at full-reset release.
36	RESET	input	Reset input: a low pulse of 200 ns to 1100 ns gives a partial reset, longer than 1250 ns gives a full reset, and holding it low powers the device down; after power-up a high pulse longer than 50 ns is required.
37	SEQEN	input	Channel sequencer enable in hardware mode (high enables, low disables); must be tied to DGND in software mode and is latched at full-reset release.
38	HW_RNGSEL1	input	Hardware/software mode select and hardware input range select (together with HW_RNGSEL0): 00 = software mode, 01 = ±2.5 V, 10 = ±5 V, 11 = ±10 V; mode is latched at full reset.
39	HW_RNGSEL0	input	Hardware/software mode select and hardware input range select (together with HW_RNGSEL1): 00 = software mode, 01 = ±2.5 V, 10 = ±5 V, 11 = ±10 V; mode is latched at full reset.
40	SER/PAR	input	Interface select: low selects the parallel interface, high selects the serial interface; latched at power-up or full-reset release.
41	DB0	bidirectional	Parallel data bit 0 (output/input); must be tied to DGND in serial mode.
42	DB1	bidirectional	Parallel data bit 1 (output/input); must be tied to DGND in serial mode.
43	DB2	bidirectional	Parallel data bit 2 (output/input); must be tied to DGND in serial mode.
44	DB3	bidirectional	Parallel data bit 3 (output/input); must be tied to DGND in serial mode.
45	DB4/SER1W	bidirectional	Parallel data bit 4 (tri-state); in serial mode selects 2-wire (high, SDOA and SDOB) or 1-wire (low, SDOA only) output and is latched at full reset.
46	DB5/CRCEN	bidirectional	Parallel data bit 5 (tri-state); in serial mode it is the CRC enable input (high appends a CRC word after conversion results), latched at full reset release and tied to DGND in software mode.
47	DB6	bidirectional	Parallel data bit 6 (tri-state); must be tied to DGND in serial mode.
48	DB7	bidirectional	Parallel data bit 7 (tri-state); must be tied to DGND in serial mode.
49	VDRIVE	power_in	Logic supply 2.3 V to 3.6 V that sets the logic interface voltage; decoupled to DGND with 0.1 µF in parallel with 10 µF.
50	DGND	power_in	Digital ground.
51	REGGNDD	power_in	Ground for the digital LDO.
52	REGCAPD	passive	Digital LDO output, typically 1.9 V; decouple to REGGNDD with a 1 µF capacitor.
53	DB8	bidirectional	Parallel data bit 8 (tri-state); must be tied to DGND in serial mode.
54	DB9	bidirectional	Parallel data bit 9 (tri-state); must be tied to DGND in serial mode.
55	DB10/SDI	bidirectional	Parallel data bit 10 (tri-state); in serial mode it is the SPI data input SDI.
56	DB11/SDOB	bidirectional	Parallel data bit 11 (tri-state); in serial mode it is the serial data output SDOB for channel B.
57	DB12/SDOA	bidirectional	Parallel data bit 12 (tri-state); in serial mode it is the serial data output SDOA for channel A.
58	DB13/OS0	bidirectional	Parallel data bit 13 (tri-state); in hardware serial mode it is oversampling control OS0, latched at full reset release.
59	DB14/OS1	bidirectional	Parallel data bit 14 (tri-state); in hardware serial mode it is oversampling control OS1, latched at full reset release.
60	DB15/OS2	bidirectional	Parallel data bit 15 (tri-state); in hardware serial mode it is oversampling control OS2, latched at full reset release.
61	WR/BURST	input	Write strobe in software parallel mode; in hardware parallel or serial mode it enables burst sequencer mode, latched at full reset release.
62	SCLK/RD	input	Serial clock input in serial mode, or read strobe (active low with CS) in parallel mode for reading the conversion data bus.
63	CS	input	Chip select: low enables the DBx output bus in parallel mode and enables serial read frames in serial mode.
64	CHSEL0	input	Channel select bit 0 for the next conversion pair in hardware mode (channel pair V0A/V0B to V7A/V7B); must be tied to DGND in software mode.
65	CHSEL1	input	Channel select bit 1 for the next conversion pair in hardware mode (channel pair V0A/V0B to V7A/V7B); must be tied to DGND in software mode.
66	CHSEL2	input	Channel select bit 2 for the next conversion pair in hardware mode (channel pair V0A/V0B to V7A/V7B); must be tied to DGND in software mode.
67	BUSY	output	Conversion status output: goes high after the CONVST rising edge and returns low when conversion completes; data must be read after BUSY falls.
68	CONVST	input	Conversion start: a low-to-high transition starts conversion of the selected analog input pair; ignored while BUSY is high.
69	REGGND	power_in	Ground for the internal analog LDO.
70	REGCAP	passive	Internal analog LDO output, typically 1.9 V; decouple to REGGND with a 1 µF capacitor.
71	VCC	power_in	Analog supply 4.75 V to 5.25 V for the front-end amplifiers and ADC core, decoupled to AGND with 0.1 µF in parallel with 10 µF.
72	AGND	power_in	Analog power ground.
73	V0B	passive	Analog input for channel 0 on ADC B; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
74	V0BGND	power_in	Analog input ground return for channel 0 input V0B (ADC B).
75	V1B	passive	Analog input for channel 1 on ADC B; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
76	V1BGND	power_in	Analog input ground return for channel 1 input V1B (ADC B).
77	V2B	passive	Analog input for channel 2 on ADC B; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
78	V2BGND	power_in	Analog input ground return for channel 2 input V2B (ADC B).
79	V3B	passive	Analog input for channel 3 on ADC B; input is bipolar ±10 V, ±5 V or ±2.5 V with 1 MΩ input impedance and clamp protection to ±19.5 V.
80	V3BGND	power_in	Analog input ground return for channel 3 input V3B (ADC B).

Key specifications

Parameter	Value
Manufacturer	CIMO
Package	LQFP-80(14x14)
Category	Data Acquisition
Pins	80

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating temperature		-40		125	°C		9
Storage temperature		-65		150	°C		9
Junction temperature				150	°C		9
Lead-tin soldering temperature				240	°C	10 s to 30 s	9
Lead-free soldering temperature				260	°C		9
VCC to AGND	VCC	-0.3		7.2	V		9
VDRIVE to AGND	VDRIVE	-0.3			V	max: VCC + 0.3 V (printed as expression)	9
Analog input voltage to AGND		-19.5		19.5	V		9
Digital input voltage to AGND		-0.3			V	max: VDRIVE + 0.3 V (printed as expression)	9
Digital output voltage to AGND		-0.3			V	max: VDRIVE + 0.3 V (printed as expression)	9
REFINOUT to AGND	REFINOUT	-0.3			V	max: VCC + 0.3 V (printed as expression)	9
ESD HBM, all pins except analog inputs				2000	V	HBM; all pins except analog inputs	9
ESD HBM, analog input pins				8000	V	HBM; analog input pins only	9
ESD CDM				750	V	CDM	9
Analog supply voltage	VCC	4.75		5.25	V		12
Digital interface supply voltage	VDRIVE	2.3		3.6	V		12
SNR	SNR	88.2	90		dB	无过采样，±10V 范围	10
SNR	SNR	87.7	89.2		dB	无过采样，±5V 范围	10
SNR	SNR	85.5	87		dB	无过采样，±2.5V 范围	10
SNDR	SNDR	87.9	89.7		dB	无过采样，±10V 范围	10
SNDR	SNDR	87.4	88.9		dB	无过采样，±5V 范围	10
SNDR	SNDR	85.2	86.7		dB	无过采样，±2.5V 范围	10
THD	THD		-105	-98	dB	无过采样，±10V 范围	10
Phase delay drift		-0.42		0.42	ns/℃	±10V 范围	10
DNL	DNL		0.6	0.99	LSB	外部基准电压源	10
INL	INL		0.8	2	LSB	外部基准电压源	11
PFS	PFS		3	20	LSB	外部基准电压源，±10V 范围	11
PFS	PFS		1	12	LSB	外部基准电压源，±5V 范围	11
PFS temperature drift	PFS	-2		2	ppm/℃	外部基准电压源	11
PFS temperature drift	PFS	-7		7	ppm/℃	内部基准电压源	11
NFS	NFS		3	20	LSB	外部基准电压源，±10V 范围	11
NFS	NFS		1	12	LSB	外部基准电压源，±5V 范围	11
NFS temperature drift	NFS	-2		2	ppm/℃	外部基准电压源	11
NFS temperature drift	NFS	-7		7	ppm/℃	内部基准电压源	11
PFS matching	PFS		8	24	LSB	±10V 范围	11
PFS matching	PFS		1	10	LSB	±5V 范围	11
NFS matching	NFS		8	24	LSB	±10V 范围	11
NFS matching	NFS		1	10	LSB	±5V 范围	11
Bipolar zero code error			1	15	LSB	±10V 范围	11
Bipolar zero code error			0.5	7	LSB	±5V 范围	11
Bipolar zero code error temperature drift		-3.5		3.5	μV/℃	±10V 范围	11
Bipolar zero code error temperature drift		-1.9		1.9	μV/℃	±5V 范围	11
Bipolar zero code error temperature drift		-1.1		1.1	μV/℃	±2.5V 范围	11
Bipolar zero code error matching			7	12	LSB	±10V 范围	11
Bipolar zero code error matching			2	6	LSB	±5V 范围	11
Reference input voltage		2.495	2.5	2.505	V		12
Reference output voltage		2.495	2.5	2.505	V		12
Reference source temperature coefficient			5	15	ppm/℃	TA = -40℃~85℃	12
Reference source temperature coefficient			7	20	ppm/℃		12
Analog supply current, standby mode	IVCC		32	35	mA	待机模式	12
Analog supply current, conversion mode	IVCC		36	40	mA	转换模式	12
Minimum time between CONVST rising edges (excluding burst and oversampling)	tCYCLE	1			μs	连续 CONVST 上升沿之间的最短时间（不包括突发和过采样模式）	13
RESET low pulse width, partial reset	tRESET_LOW	200		1100	ns	部分复位	13
RESET low pulse width, full reset	tRESET_LOW	1250			ns	完全复位	13
Time from stable VCC/VDRIVE to RESET release	tRESET_WAIT	1			ms		13
CS falling edge setup to BUSY falling edge	tCS_SETUP	20			ns	BUSY 下降沿到CS下降沿建立时间	13
CHSEL channel select setup time, hardware mode	tCH_SETUP	50			ns	硬件模式下 CHSELx 的通道选择建立时间	13

CAD (KiCad official)

Symbol: CM2249-QFPTR
Footprint: Package_QFP:LQFP-80_14x14mm_P0.65mm
3D model: LQFP-80(14x14) (KiCad packages3D, STEP)
3D model files: cm2249-qfptr-etched.step / cm2249-qfptr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cm2249-qfptr.step / cm2249-qfptr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: CIMO datasheet (41 pp, sha256 fc28061c8cda7505, retrieved 2026-10-18, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF