CM2248-QFPTR from CIMO, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVCC	power_in	Analog supply pin; decouple to AGND with 100nF in parallel with 10µF, and the AVCC supply range is 4.75 V to 5.25 V.
2	AGND	power_in	Analog ground reference for all analog circuitry; all six AGND pins must be connected to the system AGND plane.
3	OS0	input	Oversampling select LSB; together with OS1 and OS2 it sets the digital-filter oversampling ratio from no oversampling up to 64x per Table 2.
4	OS1	input	Oversampling select middle bit; together with OS0 and OS2 it sets the digital-filter oversampling ratio per Table 2.
5	OS2	input	Oversampling select MSB; OS[2:0] = 111 is stated as invalid in Table 2.
6	PAR/SER/BYTE_SEL	input	With DB15/BYTE_SEL selects the interface: low selects parallel, high with DB15/BYTE_SEL low selects serial, and high with DB15/BYTE_SEL high selects parallel byte mode.
7	STBY	input	Low-power mode input; with RANGE selects standby (RANGE high) or shutdown (RANGE low) mode.
8	RANGE	input	Selects the analog input range for all channels: high gives ±10 V and low gives ±5 V; a change takes effect immediately and about 80 µs settling is required before the next sample.
9	CONVSTA	input	Convert-start input for V1 to V4 on its rising edge; tie to CONVSTB for simultaneous sampling of all eight channels.
10	CONVSTB	input	Convert-start input for V5 to V8 on its rising edge; tie to CONVSTA for simultaneous sampling of all eight channels.
11	RESET	input	Active-high reset that aborts any conversion in progress and clears the output register to all zeros; after power-up a high pulse longer than 50 ns is required.
12	RD/SCLK	input	Parallel read strobe RD in parallel interface mode, or serial clock SCLK in serial interface mode.
13	CS	input	Active-low chip select that enables data frame transfer.
14	BUSY	output	Goes high once CONVSTA and CONVSTB have both gone high and stays high until all channel conversions finish; its falling edge latches the conversion data into the output registers.
15	FRSTDATA	output	Indicates that the first channel V1 result is ready to be read back; it is tri-stated while CS is high.
16	DB0	output	Parallel data bit 0 (LSB) of the conversion result; must be connected to AGND when PAR/SER/BYTE_SEL is high.
17	DB1	output	Parallel data bit 1 of the conversion result; must be connected to AGND when PAR/SER/BYTE_SEL is high.
18	DB2	output	Parallel data bit 2 of the conversion result; must be connected to AGND when PAR/SER/BYTE_SEL is high.
19	DB3	output	Parallel data bit 3 of the conversion result; must be connected to AGND when PAR/SER/BYTE_SEL is high.
20	DB4	output	Parallel data bit 4 of the conversion result; must be connected to AGND when PAR/SER/BYTE_SEL is high.
21	DB5	output	Parallel data bit 5 of the conversion result; must be connected to AGND when PAR/SER/BYTE_SEL is high.
22	DB6	output	Parallel data bit 6 of the conversion result; must be connected to AGND when PAR/SER/BYTE_SEL is high.
23	VDRIVE	power_in	Logic interface supply, 1.7 V to 5.25 V; it should match the supply of the controller (DSP or FPGA) it interfaces with.
24	DB7/DOUTA	output	Parallel data bit 7 (MSB in parallel mode) or serial data output DOUTA.
25	DB8/DOUTB	output	Parallel data bit 8 or serial data output DOUTB.
26	AGND	power_in	Analog ground; connect to the system AGND plane.
27	DB9	output	Parallel data bit 9 of the conversion result; must be connected to AGND when PAR/SER/BYTE_SEL is high.
28	DB10	output	Parallel data bit 10 of the conversion result; must be connected to AGND when PAR/SER/BYTE_SEL is high.
29	DB11	output	Parallel data bit 11 of the conversion result; must be connected to AGND when PAR/SER/BYTE_SEL is high.
30	DB12	output	Parallel data bit 12 of the conversion result; must be connected to AGND when PAR/SER/BYTE_SEL is high.
31	DB13	output	Parallel data bit 13 of the conversion result; must be connected to AGND when PAR/SER/BYTE_SEL is high.
32	DB14/HBEN	bidirectional	Parallel data bit 14 in parallel mode; in parallel byte mode it selects MSB-first (HBEN = 1) or LSB-first (HBEN = 0) output, and must be tied to AGND when PAR/SER/BYTE_SEL is high outside byte mode.
33	DB15/BYTE_SEL	bidirectional	Parallel data bit 15 (MSB) in parallel mode; when PAR/SER/BYTE_SEL is high it selects serial (0) or parallel byte (1) interface.
34	REF_SELECT	input	Selects the internal 2.5 V reference when high; when low the internal reference is disabled and an external 2.5 V reference must be applied to REFIN/REFOUT.
35	AGND	power_in	Analog ground; connect to the system AGND plane.
36	REGCAP	power_out	Internal regulator output at about 1.9 V; decouple to AGND with 1 µF, and must not be tied directly to pin 39.
37	AVCC	power_in	Analog supply pin, 4.75 V to 5.25 V; decouple to AGND with 100nF in parallel with 10µF (may share the decoupling capacitor with pin 38).
38	AVCC	power_in	Analog supply pin, 4.75 V to 5.25 V; decouple to AGND with 100nF in parallel with 10µF (may share the decoupling capacitor with pin 37).
39	REGCAP	power_out	Internal regulator output at about 1.9 V; decouple to AGND with 1 µF, and must not be tied directly to pin 36.
40	AGND	power_in	Analog ground; connect to the system AGND plane.
41	AGND	power_in	Analog ground; connect to the system AGND plane.
42	REFIN/REFOUT	bidirectional	Outputs a 2.5 V internal reference when REF_SELECT is high or accepts a 2.5 V external reference when REF_SELECT is low; a 10 µF capacitor to REFGND is required in both cases.
43	REFGND	power_in	Reference ground; connect to AGND.
44	REFCAPA	passive	Reference buffer output at about 4 V; must be shorted to REFCAPB and decoupled to AGND with a 10 µF low-ESR ceramic capacitor.
45	REFCAPB	passive	Reference buffer output at about 4 V; must be shorted to REFCAPA and decoupled to AGND with a 10 µF low-ESR ceramic capacitor.
46	REFGND	power_in	Reference ground; connect to AGND.
47	AGND	power_in	Analog ground; connect to the system AGND plane.
48	AVCC	power_in	Analog supply pin, 4.75 V to 5.25 V; decouple to AGND with 100nF in parallel with 10µF.
49	V1	passive	Single-ended bipolar analog input whose range (±10 V or ±5 V) is set by RANGE; input impedance is 1 MΩ and the clamp protects to ±18.5 V.
50	V1GND	power_in	Ground return for analog input V1; connect to the system AGND plane.
51	V2	passive	Single-ended bipolar analog input whose range (±10 V or ±5 V) is set by RANGE; input impedance is 1 MΩ and the clamp protects to ±18.5 V.
52	V2GND	power_in	Ground return for analog input V2; connect to the system AGND plane.
53	V3	passive	Single-ended bipolar analog input whose range (±10 V or ±5 V) is set by RANGE; input impedance is 1 MΩ and the clamp protects to ±18.5 V.
54	V3GND	power_in	Ground return for analog input V3; connect to the system AGND plane.
55	V4	passive	Single-ended bipolar analog input whose range (±10 V or ±5 V) is set by RANGE; input impedance is 1 MΩ and the clamp protects to ±18.5 V.
56	V4GND	power_in	Ground return for analog input V4; connect to the system AGND plane.
57	V5	passive	Single-ended bipolar analog input whose range (±10 V or ±5 V) is set by RANGE; input impedance is 1 MΩ and the clamp protects to ±18.5 V.
58	V5GND	power_in	Ground return for analog input V5; connect to the system AGND plane.
59	V6	passive	Single-ended bipolar analog input whose range (±10 V or ±5 V) is set by RANGE; input impedance is 1 MΩ and the clamp protects to ±18.5 V.
60	V6GND	power_in	Ground return for analog input V6; connect to the system AGND plane.
61	V7	passive	Single-ended bipolar analog input whose range (±10 V or ±5 V) is set by RANGE; input impedance is 1 MΩ and the clamp protects to ±18.5 V.
62	V7GND	power_in	Ground return for analog input V7; connect to the system AGND plane.
63	V8	passive	Single-ended bipolar analog input whose range (±10 V or ±5 V) is set by RANGE; input impedance is 1 MΩ and the clamp protects to ±18.5 V.
64	V8GND	power_in	Ground return for analog input V8; connect to the system AGND plane.

Key specifications

Parameter	Value
Manufacturer	CIMO
Package	LQFP-64(10x10)
Category	ADC/DAC/Data Conversion
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
SNR	SNR	89.5	92		dB	±10V 单端	9
SNR	SNR	88.5	91		dB	±5V 单端	9
SINAD	SINAD	89.2	92		dB	±10V 单端	9
SINAD	SINAD	88.2	91		dB	±5V 单端	9
SFDR	SFDR	96	108		dB	±10V 单端	9
THD	THD	-105	-95		dB	±10V 单端	9
DNL	DNL	-0.99		0.99	LSB	16bit	9
INL	INL	-2		2	LSB	16bit	9
PFS	PFS	-20		20	LSB	外部基准电压源	9
PFS 匹配		2	8		LSB	±10V 范围	9
PFS 匹配		6	16		LSB	±5V 范围	9
PFS 漂移		-2		2	ppm/℃	外部基准电压源	9
PFS 漂移		-8		8	ppm/℃	内部基准电压源	9
NFS	NFS	-20		20	LSB	外部基准电压源	9
NFS 匹配		2	8		LSB	±10V 范围	9
NFS 匹配		6	16		LSB	±5V 范围	9
NFS 漂移		-2		2	ppm/℃	外部基准电压源	9
NFS 漂移		-8		8	ppm/℃	内部基准电压源	9
双极性 0 码误差		-4		4	LSB	±10V 范围	9
双极性 0 码误差		-12		12	LSB	±5V 范围	9
双极性 0 码误差匹配		1	6		LSB	±10V 范围	9
双极性 0 码误差匹配		6	15		LSB	±5V 范围	9
基准输入电压范围		2.475	2.5	2.525	V		10
基准源温度系数		-7		7	ppm/℃		10
AVCC 电源电压	AVCC	4.75		5.25	V		10
VDRIVE 电源电压	VDRIVE	1.7		5.25	V		10
IAVCC 关断模式	IAVCC	1	3		μA		10
IAVCC 待机模式	IAVCC	5.7	8.5		mA		10
IAVCC 静态模式	IAVCC	16.5	23		mA		10
IAVCC 转换模式	IAVCC	21.5	28		mA	fSAMPLE = 200kSPS	10
最短 CONVSTx 低电平脉冲	tLP_CNV	10			ns		11
最短 CONVSTx 高电平脉冲	tHP_CNV	10			ns		11
RESET 低电平到 CONVSTx 高电平之间的最短延迟时间	tDEVICE_SETUP	25			ns		11
最后CS上升沿与 BUSY 下降沿之间的最长时间	tD_BSY			25	ns		11
CONVSTA/B 上升沿之间最大容许延迟时间	tCNV_DLY			0.5	ms		11
工作温度		-40		125	℃		8
存储温度		-65		150	℃		8
结温				150	℃		8
铅锡焊接温度				240	℃	10 秒到 30 秒	8
无铅焊接温度				260	℃		8
AVCC 至 AGND		-0.3		7	V		8
模拟输入至 AGND		-18.5		18.5	V		8
输入电流		-10		10	mA	只针对除电源管脚外任意管脚	8
VDRIVE 至 AGND		-0.3			V		8
数字输入至 AGND		-0.3			V		8
数字输出至 AGND		-0.3			V		8
REFIN 至 AGND		-0.3			V		8

CAD (KiCad official)

Symbol: CM2248-QFPTR
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: cm2248-qfptr-etched.step / cm2248-qfptr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cm2248-qfptr.step / cm2248-qfptr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: CIMO datasheet (27 pp, sha256 cb7e3944fcbcc7a7, retrieved 2026-11-13, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CM2248-QFPTR

Verified CM2248-QFPTR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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