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CM1341-KKT

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by adom

iCM(创芯微) Battery Management, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CM1341-KKT

iCM(创芯微) · Battery Management · TSSOP-16

CM1341-KKT from iCM(创芯微), in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Positive supply input and connection for battery 1 positive terminal; absolute maximum rating is VSS-0.3 V to VSS+40 V.
2 VNC passive Battery 1 positive voltage connection terminal (printed as VNC in the datasheet); absolute maximum rating for cell terminals is VSS-0.3 V to VSS+40 V.
3 VNC passive Battery 1 positive voltage connection terminal (printed as VNC in the datasheet); absolute maximum rating for cell terminals is VSS-0.3 V to VSS+40 V.
4 VNC passive Battery 1 positive voltage connection terminal (printed as VNC in the datasheet); absolute maximum rating for cell terminals is VSS-0.3 V to VSS+40 V.
5 VC1 power_in Battery 1 positive voltage connection terminal for cell voltage sensing; absolute maximum rating is VSS-0.3 V to VSS+40 V.
6 VC2 power_in Battery 1 negative voltage and battery 2 positive voltage connection terminal for cell voltage sensing; absolute maximum rating is VSS-0.3 V to VSS+40 V.
7 VC3 power_in Battery 2 negative voltage and battery 3 positive voltage connection terminal for cell voltage sensing; absolute maximum rating is VSS-0.3 V to VSS+40 V.
8 VC4 power_in Battery 3 negative voltage and battery 4 positive voltage connection terminal for cell voltage sensing; absolute maximum rating is VSS-0.3 V to VSS+40 V.
9 VSS power_in Chip ground and battery 4 negative voltage connection terminal; it is the reference for all absolute maximum ratings.
10 TEC input Discharge overcurrent delay adjustment terminal, where the external capacitor CTEC sets TEC1 = 10 × CTEC (nF) ms; absolute maximum rating is VSS-0.3 V to VSS+5.5 V.
11 RTS input Connects to the NTC thermistor (B = 3950, 100 kΩ at 25 °C) for temperature detection; absolute maximum rating is VSS-0.3 V to VCC+0.3 V.
12 RTV input Connects to a resistor to RTS to set the high-temperature protection threshold (RT = 3 × RNTC at TCH); absolute maximum rating is VSS-0.3 V to VSS+5.5 V.
13 VINI input Overcurrent detection input sensing the discharge and charge current voltage; absolute maximum rating is VSS-0.3 V to VCC+0.3 V.
14 DO output Discharge MOSFET control output, which turns off the discharge MOS on fault; absolute maximum rating is VSS-0.3 V to VCC+0.3 V.
15 CO output Charge MOSFET control output, which turns off the charge MOS on fault; absolute maximum rating is VSS-15 V to VCC+0.3 V.
16 VM input Charger and load detection terminal; absolute maximum rating is VSS-15 V to VCC+0.3 V.

Key specifications

Parameter Value
Manufacturer iCM(创芯微)
Package TSSOP-16
Category Power Management (PMIC)
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Normal operating current (IVCC) IVCC 10 15 μA Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V 6
Overcharge protection voltage VOC 3.635 3.65 3.665 V Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5 → 4.4V 6
Overcharge release voltage VOCR 3.52 3.55 3.58 V Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 4.4 → 3.5V 6
Overcharge protection delay TOC 0.7 1 1.3 s Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5 → 4.4V 6
Overcharge release delay TOCR 128 256 384 ms Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 4.4 → 3.5V 6
Balance start voltage VBAL 3.5 3.525 3.55 V Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5 → 4.4V 6
Overdischarge protection voltage VOD 2.25 2.3 2.35 V Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5 → 2.0V 6
Overdischarge release voltage VODR 2.42 2.5 2.58 V Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 2.0 → 3.5V 6
Overdischarge protection delay TOD 0.7 1 1.3 s Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5 → 2.0V 6
Overdischarge release delay TODR 128 256 384 ms Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 2.0 → 3.5V 6
Discharge overcurrent 1 protection voltage VEC1 0.045 0.05 0.055 V Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → 0.18V 6
Discharge overcurrent 1 protection delay TEC1 0.5 1 1.5 s Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → 0.18V, CTEC=0.1μF 6
Discharge overcurrent 2 protection voltage VEC2 0.085 0.1 0.115 V Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → 0.35V 6
Discharge overcurrent 2 protection delay TEC2 50 100 150 ms Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → 0.35V, CTEC=0.1μF 6
Short-circuit protection voltage VSHORT 0.16 0.2 0.24 V Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → 0.8V 7
Short-circuit protection delay TSHORT 100 300 500 μs Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → 0.8V 7
Discharge overcurrent release delay TECR 22 32 42 ms Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0.8 → 0V 7
Charge overcurrent protection voltage VCHA -0.055 -0.05 -0.045 V Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → -1.0V 7
Charge overcurrent protection delay TCHA 180 256 332 ms Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → -1.0V 7
Charge overcurrent release delay TCHAR 45 64 83 ms Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = -1V → 0V 7
Open-wire protection delay TOW 4 s Ta = +25°C; CVC1~4=0.1μF 7
Charge high-temperature protection temperature (nominal TCH set by RT, offset) TCH -3 3 °C Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 100k → 10k 7
Charge high-temperature release temperature (nominal TCHR, offset) TCHR -3 3 °C Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 10k → 100k 7
Discharge high-temperature protection temperature (nominal TDH, offset) TDH -3 3 °C Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 100k → 10k 7
Discharge high-temperature release temperature (nominal TDHR, offset) TDHR -3 3 °C Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 10k → 100k 7
Charge high-temperature protection delay DTCH 0.7 1 1.3 s Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 100k → 10k 7
Charge high-temperature release delay DTCHR 90 128 166 ms Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 10k → 100k 7
Discharge high-temperature protection delay DTDH 0.7 1 1.3 s Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 100k → 10k 7
Discharge high-temperature release delay DTDHR 90 128 166 ms Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 10k → 100k 7
Charge low-temperature protection temperature (nominal TCL, offset) TCL -3 3 °C Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 100k → 3M 7
Charge low-temperature release temperature (nominal TCLR, offset) TCLR -3 3 °C Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 3M → 100k 7
Discharge low-temperature protection temperature (nominal TDL, offset) TDL -3 3 °C Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 100k → 3M 7
Discharge low-temperature release temperature (nominal TDLR, offset) TDLR -3 3 °C Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 3M → 100k 8
Charge low-temperature protection delay DTCL 0.7 1 1.3 s Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 100k → 3M 8
Charge low-temperature release delay DTCLR 90 128 166 ms Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 3M → 100k 8
Discharge low-temperature protection delay DTDL 0.7 1 1.3 s Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 100k → 3M 8
Discharge low-temperature release delay DTDLR 90 128 166 ms Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, RNTC = 3M → 100k 8
Discharge state detection voltage VSTS 1 4 7 mV Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → 10mV 8
Discharge state detection delay TSTS 3 4.5 6 ms Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → 10mV 8
Sleep delay TSLP 22 32 42 s Ta = +25°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5 → 1.5V 8
Normal operating current (IVCC) IVCC 10 20 μA Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V 9
Overcharge protection voltage VOC 3.61 3.65 3.69 V Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5 → 4.4V 9
Overcharge release voltage VOCR 3.49 3.55 3.61 V Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 4.4 → 3.5V 9
Overcharge protection delay TOC 0.5 1 1.5 s Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5 → 4.4V 9
Balance start voltage VBAL 3.475 3.525 3.575 V Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5 → 4.4V 9
Overdischarge protection voltage VOD 2.2 2.3 2.4 V Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5 → 2.0V 9
Overdischarge release voltage VODR 2.35 2.5 2.65 V Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 2.0 → 3.5V 9
Discharge overcurrent 1 protection voltage VEC1 0.042 0.05 0.058 V Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → 0.18V 9
Discharge overcurrent 2 protection voltage VEC2 0.08 0.1 0.12 V Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → 0.35V 9
Short-circuit protection voltage VSHORT 0.14 0.2 0.26 V Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → 0.8V 10
Charge overcurrent protection voltage VCHA -0.058 -0.05 -0.042 V Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → -1.0V 10
Discharge state detection voltage VSTS 1 4 7 mV Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5V, VINI = 0 → 10mV 11
Sleep delay TSLP 16 32 48 s Ta = -40°C ~ +85°C; VCn - VCn+1 = 3.5V, VC4-VSS = 3.5 → 1.5V 11
Supply voltage VCC -0.3 40 V Referenced to VSS (printed VSS-0.3 ~ VSS+40) 5
Input voltage 0 (cell terminals VCn) VCELL -0.3 40 V Referenced to VSS (printed VSS-0.3 ~ VSS+40); terminals VCn, n=1~4 5
Input voltage 1 (RTV, TEC) VIN1 -0.3 5.5 V Referenced to VSS (printed VSS-0.3 ~ VSS+5.5) 5
Input voltage 2 (VM, CO) VIN2 -15 0.3 V Min referenced to VSS (VSS-15); max referenced to VCC (VCC+0.3) 5
Input voltage 3 (DO, RTS, VINI) VIN3 -0.3 0.3 V Min referenced to VSS (VSS-0.3); max referenced to VCC (VCC+0.3) 5
Operating ambient temperature TOPR -40 85 °C 5
Storage temperature range TSTG -55 125 °C 5

CAD (KiCad official)

  • Symbol: CM1341-KKT
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cm1341-kkt-etched.step / cm1341-kkt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cm1341-kkt.step / cm1341-kkt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: iCM(创芯微) datasheet (20 pp, sha256 17a741080ba5fd15, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF