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CM1250-BNA-M8A
Public Made by Adomby adom
iCM(创芯微) Battery Management, MSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CM1250-BNA-M8A
iCM(创芯微) · Battery Management · MSOP-8
CM1250-BNA-M8A from iCM(创芯微), in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Chip supply terminal, rated VSS-0.3 V to VSS+30 V absolute maximum, with normal-mode current of 3.5 µA typical at Ta = +25 °C. |
| 2 | VC1 | input | Positive voltage terminal of battery cell 1 for overcharge detection, rated 0 to 12 V absolute maximum per cell. |
| 3 | VC2 | input | Positive voltage terminal of battery cell 2 and negative voltage terminal of cell 1 for overcharge detection, rated 0 to 12 V absolute maximum per cell. |
| 4 | VC3 | input | Positive voltage terminal of battery cell 3 and negative voltage terminal of cell 2 for overcharge detection, rated 0 to 12 V absolute maximum per cell. |
| 5 | VC4 | input | Positive voltage terminal of battery cell 4 and negative voltage terminal of cell 3 for overcharge detection, rated 0 to 12 V absolute maximum per cell. |
| 6 | VC5 | input | Positive voltage terminal of battery cell 5 and negative voltage terminal of cell 4 for overcharge detection, rated 0 to 12 V absolute maximum per cell. |
| 7 | VSS | power_in | Negative voltage terminal of battery cell 5 and chip ground, the reference for the VCC and CO absolute maximum ratings. |
| 8 | CO | output | Charge-control output that drives the external MOSFET, rated VSS-0.3 V to VCC+0.3 V absolute maximum; this M8A variant (CM1250-BNA-M8A) is specified with a 10.5 V high-level output potential. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | iCM(创芯微) |
| Package | MSOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply current (VCC) | IVCC | 3.5 | 5.5 | μA | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 8 | |
| Current into VC2 | IVC2 | 0 | 0.8 | 1.5 | μA | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 8 |
| Current into VC3 | IVC3 | -1.5 | -0.8 | 0 | μA | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 8 |
| Current into VC4 | IVC4 | 0 | 0.8 | 1.5 | μA | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 8 |
| Current into VC5 | IVC5 | -1.5 | -0.8 | 0 | μA | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 8 |
| Overcharge release voltage (offset from VOCR; VOC-VOCR<0.250V row) | VOCR | -0.05 | 0.05 | V | Ta=+25°C; VOC-VOCR<0.250V; VC1=VC2=VC3=VC4=3.5V, VC5=4.4→3.5V | 8 | |
| Overcharge protection delay (multiple of Toc=1 s) | TOC | 1 | s | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5→4.4V | 8 | ||
| Overcharge recovery delay | TOCR | 180 | 256 | 332 | ms | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=4.4→3.5V | 8 |
| Reset delay | TTR | 1.5 | 2.5 | 3.5 | ms | Ta=+25°C | 8 |
| CO high-level output potential (10.5 V option) | VCOH | 10.5 | V | Ta=+25°C | 8 | ||
| CO sink current (CMOS product) | ICOL | 0.4 | mA | Ta=+25°C | 8 | ||
| CO source current (CMOS product) | ICOH | 50 | μA | Ta=+25°C | 8 | ||
| Supply current (VCC) | IVCC | 3.5 | 7 | μA | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 9 | |
| Current into VC2 | IVC2 | 0 | 0.8 | 1.8 | μA | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 9 |
| Current into VC3 | IVC3 | -1.8 | -0.8 | 0 | μA | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 9 |
| Current into VC4 | IVC4 | 0 | 0.8 | 1.8 | μA | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 9 |
| Current into VC5 | IVC5 | -1.8 | -0.8 | 0 | μA | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 9 |
| Overcharge release voltage (offset from VOCR; VOC-VOCR<0.250V row) | VOCR | -0.08 | 0.08 | V | Ta=-20°C~+60°C; VOC-VOCR<0.250V; VC1=VC2=VC3=VC4=3.5V, VC5=4.4→3.5V | 9 | |
| Overcharge protection delay (multiple of Toc=1 s) | TOC | 1 | s | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5→4.4V | 9 | ||
| Overcharge recovery delay | TOCR | 154 | 256 | 358 | ms | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=4.4→3.5V | 9 |
| Reset delay | TTR | 1 | 2.5 | 4 | ms | Ta=-20°C~+60°C | 9 |
| CO high-level output potential (10.5 V option) | VCOH | 10.5 | V | Ta=-20°C~+60°C | 9 | ||
| CO sink current (CMOS product) | ICOL | 0.4 | mA | Ta=-20°C~+60°C | 9 | ||
| CO source current (CMOS product) | ICOH | 50 | μA | Ta=-20°C~+60°C | 9 | ||
| Supply current (VCC) | IVCC | 3.5 | 8 | μA | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 10 | |
| Current into VC2 | IVC2 | 0 | 0.8 | 2 | μA | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 10 |
| Current into VC3 | IVC3 | -2 | -0.8 | 0 | μA | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 10 |
| Current into VC4 | IVC4 | 0 | 0.8 | 2 | μA | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 10 |
| Current into VC5 | IVC5 | -2 | -0.8 | 0 | μA | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 10 |
| Overcharge release voltage (offset from VOCR; VOC-VOCR<0.250V row) | VOCR | -0.1 | 0.1 | V | Ta=-40°C~+85°C; VOC-VOCR<0.250V; VC1=VC2=VC3=VC4=3.5V, VC5=4.4→3.5V | 10 | |
| Overcharge protection delay (multiple of Toc=1 s) | TOC | 1 | s | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5→4.4V | 10 | ||
| Overcharge recovery delay | TOCR | 128 | 256 | 385 | ms | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=4.4→3.5V | 10 |
| Reset delay | TTR | 0.5 | 2.5 | 5 | ms | Ta=-40°C~+85°C | 10 |
| CO high-level output potential (10.5 V option) | VCOH | 10.5 | V | Ta=-40°C~+85°C | 10 | ||
| CO sink current (CMOS product) | ICOL | 0.4 | mA | Ta=-40°C~+85°C | 10 | ||
| CO source current (CMOS product) | ICOH | 50 | μA | Ta=-40°C~+85°C | 10 | ||
| Supply voltage (VCC, relative to VSS) | VCC | -0.3 | 30 | V | 7 | ||
| Cell voltage (VC1-VC2, VC2-VC3, VC3-VC4, VC4-VC5, VC5-VSS) | VCELL | 0 | 12 | V | VC1-VC2, VC2-VC3, VC3-VC4, VC4-VC5, VC5-VSS | 7 | |
| CO output terminal voltage (min relative to VSS, max relative to VCC) | VCO | -0.3 | 0.3 | V | CO terminal | 7 | |
| Operating ambient temperature | TOPR | -40 | 85 | °C | 7 | ||
| Storage temperature | TSTG | -55 | 125 | °C | 7 |
CAD (KiCad official)
- Symbol:
CM1250-BNA-M8A - Footprint:
Package_SO:MSOP-8_3x3mm_P0.65mm - 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files:
cm1250-bna-m8a-etched.step/cm1250-bna-m8a-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cm1250-bna-m8a.step/cm1250-bna-m8a.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: iCM(创芯微) datasheet (20 pp, sha256
e17bbdf556faad96, retrieved 2026-11-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CM1250-BNA-M8A
**iCM(创芯微)** · Battery Management · MSOP-8
CM1250-BNA-M8A from iCM(创芯微), in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Chip supply terminal, rated VSS-0.3 V to VSS+30 V absolute maximum, with normal-mode current of 3.5 µA typical at Ta = +25 °C. |
| 2 | VC1 | input | Positive voltage terminal of battery cell 1 for overcharge detection, rated 0 to 12 V absolute maximum per cell. |
| 3 | VC2 | input | Positive voltage terminal of battery cell 2 and negative voltage terminal of cell 1 for overcharge detection, rated 0 to 12 V absolute maximum per cell. |
| 4 | VC3 | input | Positive voltage terminal of battery cell 3 and negative voltage terminal of cell 2 for overcharge detection, rated 0 to 12 V absolute maximum per cell. |
| 5 | VC4 | input | Positive voltage terminal of battery cell 4 and negative voltage terminal of cell 3 for overcharge detection, rated 0 to 12 V absolute maximum per cell. |
| 6 | VC5 | input | Positive voltage terminal of battery cell 5 and negative voltage terminal of cell 4 for overcharge detection, rated 0 to 12 V absolute maximum per cell. |
| 7 | VSS | power_in | Negative voltage terminal of battery cell 5 and chip ground, the reference for the VCC and CO absolute maximum ratings. |
| 8 | CO | output | Charge-control output that drives the external MOSFET, rated VSS-0.3 V to VCC+0.3 V absolute maximum; this M8A variant (CM1250-BNA-M8A) is specified with a 10.5 V high-level output potential. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | iCM(创芯微) |
| Package | MSOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply current (VCC) | IVCC | | 3.5 | 5.5 | μA | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 8 |
| Current into VC2 | IVC2 | 0 | 0.8 | 1.5 | μA | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 8 |
| Current into VC3 | IVC3 | -1.5 | -0.8 | 0 | μA | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 8 |
| Current into VC4 | IVC4 | 0 | 0.8 | 1.5 | μA | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 8 |
| Current into VC5 | IVC5 | -1.5 | -0.8 | 0 | μA | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 8 |
| Overcharge release voltage (offset from VOCR; VOC-VOCR<0.250V row) | VOCR | -0.05 | | 0.05 | V | Ta=+25°C; VOC-VOCR<0.250V; VC1=VC2=VC3=VC4=3.5V, VC5=4.4→3.5V | 8 |
| Overcharge protection delay (multiple of Toc=1 s) | TOC | | 1 | | s | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5→4.4V | 8 |
| Overcharge recovery delay | TOCR | 180 | 256 | 332 | ms | Ta=+25°C; VC1=VC2=VC3=VC4=3.5V, VC5=4.4→3.5V | 8 |
| Reset delay | TTR | 1.5 | 2.5 | 3.5 | ms | Ta=+25°C | 8 |
| CO high-level output potential (10.5 V option) | VCOH | | 10.5 | | V | Ta=+25°C | 8 |
| CO sink current (CMOS product) | ICOL | 0.4 | | | mA | Ta=+25°C | 8 |
| CO source current (CMOS product) | ICOH | 50 | | | μA | Ta=+25°C | 8 |
| Supply current (VCC) | IVCC | | 3.5 | 7 | μA | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 9 |
| Current into VC2 | IVC2 | 0 | 0.8 | 1.8 | μA | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 9 |
| Current into VC3 | IVC3 | -1.8 | -0.8 | 0 | μA | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 9 |
| Current into VC4 | IVC4 | 0 | 0.8 | 1.8 | μA | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 9 |
| Current into VC5 | IVC5 | -1.8 | -0.8 | 0 | μA | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 9 |
| Overcharge release voltage (offset from VOCR; VOC-VOCR<0.250V row) | VOCR | -0.08 | | 0.08 | V | Ta=-20°C~+60°C; VOC-VOCR<0.250V; VC1=VC2=VC3=VC4=3.5V, VC5=4.4→3.5V | 9 |
| Overcharge protection delay (multiple of Toc=1 s) | TOC | | 1 | | s | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5→4.4V | 9 |
| Overcharge recovery delay | TOCR | 154 | 256 | 358 | ms | Ta=-20°C~+60°C; VC1=VC2=VC3=VC4=3.5V, VC5=4.4→3.5V | 9 |
| Reset delay | TTR | 1 | 2.5 | 4 | ms | Ta=-20°C~+60°C | 9 |
| CO high-level output potential (10.5 V option) | VCOH | | 10.5 | | V | Ta=-20°C~+60°C | 9 |
| CO sink current (CMOS product) | ICOL | 0.4 | | | mA | Ta=-20°C~+60°C | 9 |
| CO source current (CMOS product) | ICOH | 50 | | | μA | Ta=-20°C~+60°C | 9 |
| Supply current (VCC) | IVCC | | 3.5 | 8 | μA | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 10 |
| Current into VC2 | IVC2 | 0 | 0.8 | 2 | μA | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 10 |
| Current into VC3 | IVC3 | -2 | -0.8 | 0 | μA | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 10 |
| Current into VC4 | IVC4 | 0 | 0.8 | 2 | μA | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 10 |
| Current into VC5 | IVC5 | -2 | -0.8 | 0 | μA | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5V | 10 |
| Overcharge release voltage (offset from VOCR; VOC-VOCR<0.250V row) | VOCR | -0.1 | | 0.1 | V | Ta=-40°C~+85°C; VOC-VOCR<0.250V; VC1=VC2=VC3=VC4=3.5V, VC5=4.4→3.5V | 10 |
| Overcharge protection delay (multiple of Toc=1 s) | TOC | | 1 | | s | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=3.5→4.4V | 10 |
| Overcharge recovery delay | TOCR | 128 | 256 | 385 | ms | Ta=-40°C~+85°C; VC1=VC2=VC3=VC4=3.5V, VC5=4.4→3.5V | 10 |
| Reset delay | TTR | 0.5 | 2.5 | 5 | ms | Ta=-40°C~+85°C | 10 |
| CO high-level output potential (10.5 V option) | VCOH | | 10.5 | | V | Ta=-40°C~+85°C | 10 |
| CO sink current (CMOS product) | ICOL | 0.4 | | | mA | Ta=-40°C~+85°C | 10 |
| CO source current (CMOS product) | ICOH | 50 | | | μA | Ta=-40°C~+85°C | 10 |
| Supply voltage (VCC, relative to VSS) | VCC | -0.3 | | 30 | V | | 7 |
| Cell voltage (VC1-VC2, VC2-VC3, VC3-VC4, VC4-VC5, VC5-VSS) | VCELL | 0 | | 12 | V | VC1-VC2, VC2-VC3, VC3-VC4, VC4-VC5, VC5-VSS | 7 |
| CO output terminal voltage (min relative to VSS, max relative to VCC) | VCO | -0.3 | | 0.3 | V | CO terminal | 7 |
| Operating ambient temperature | TOPR | -40 | | 85 | °C | | 7 |
| Storage temperature | TSTG | -55 | | 125 | °C | | 7 |
## CAD (KiCad official)
- Symbol: `CM1250-BNA-M8A`
- Footprint: `Package_SO:MSOP-8_3x3mm_P0.65mm`
- 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files: `cm1250-bna-m8a-etched.step` / `cm1250-bna-m8a-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cm1250-bna-m8a.step` / `cm1250-bna-m8a.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [iCM(创芯微) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603349792009838592) (20 pp, sha256 `e17bbdf556faad96`, retrieved 2026-11-07, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cm1250-bna-m8a-datasheet.pdf)