CM1213A-04SO

UMW · ESD And Surge Protection (TVS/ESD) · SOT-23-6

CM1213A-04SO from UMW, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CH1	bidirectional	ESD-protected I/O channel 1, one of the four data lines; the datasheet gives 0.35 pF typical capacitance I/O to I/O and nA-level leakage.
2	VN	passive	Negative reference pin of the reverse working voltage pair VP-VN (VRWM rated up to 5.5 V); the datasheet does not state its supply or ground role.
3	CH2	bidirectional	ESD-protected I/O channel 2, one of the four data lines; the datasheet gives 0.35 pF typical capacitance I/O to I/O and nA-level leakage.
4	CH4	bidirectional	ESD-protected I/O channel 4, one of the four data lines; the datasheet gives 0.35 pF typical capacitance I/O to I/O and nA-level leakage.
5	VP	passive	Positive reference pin of the reverse working voltage pair VP-VN (VRWM rated up to 5.5 V); the datasheet does not state its supply or ground role.
6	CH3	bidirectional	ESD-protected I/O channel 3, one of the four data lines; the datasheet gives 0.35 pF typical capacitance I/O to I/O and nA-level leakage.

Key specifications

Parameter	Value
Manufacturer	UMW
Package	SOT-23-6
Category	Circuit Protection
Pins	6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Junction Temperature Range	TJ	-55		125	°C		1
Storage Temperature Range	TSTG	-55		150	°C		1
ESD per IEC 61000-4-2 (Air)	VESD	-25		25	kV		1
ESD per IEC 61000-4-2 (Contact)	VESD	-25		25	kV		1
Reverse Working Voltage (VP-VN)	VRWM			5.5	V		2
Breakdown Voltage	VBR	6			V	IT=1mA, any I/O pin to ground	2
Junction capacitance (between I/O pins)	CJ		0.35		pF	VR=0V, f=1MHz, between I/O pins	2

CAD (KiCad official)

Symbol: CM1213A-04SO
Footprint: Package_TO_SOT_SMD:SOT-23-6
3D model: SOT-23-6 (KiCad packages3D, STEP)
3D model files: cm1213a-04so-etched.step / cm1213a-04so-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cm1213a-04so.step / cm1213a-04so.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: UMW datasheet (6 pp, sha256 e481409719beb94f, retrieved 2026-10-17, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# CM1213A-04SO

**UMW** · ESD And Surge Protection (TVS/ESD) · SOT-23-6

CM1213A-04SO from UMW, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CH1 | bidirectional | ESD-protected I/O channel 1, one of the four data lines; the datasheet gives 0.35 pF typical capacitance I/O to I/O and nA-level leakage. |
| 2 | VN | passive | Negative reference pin of the reverse working voltage pair VP-VN (VRWM rated up to 5.5 V); the datasheet does not state its supply or ground role. |
| 3 | CH2 | bidirectional | ESD-protected I/O channel 2, one of the four data lines; the datasheet gives 0.35 pF typical capacitance I/O to I/O and nA-level leakage. |
| 4 | CH4 | bidirectional | ESD-protected I/O channel 4, one of the four data lines; the datasheet gives 0.35 pF typical capacitance I/O to I/O and nA-level leakage. |
| 5 | VP | passive | Positive reference pin of the reverse working voltage pair VP-VN (VRWM rated up to 5.5 V); the datasheet does not state its supply or ground role. |
| 6 | CH3 | bidirectional | ESD-protected I/O channel 3, one of the four data lines; the datasheet gives 0.35 pF typical capacitance I/O to I/O and nA-level leakage. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOT-23-6 |
| Category | Circuit Protection |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Junction Temperature Range | TJ | -55 |  | 125 | °C |  | 1 |
| Storage Temperature Range | TSTG | -55 |  | 150 | °C |  | 1 |
| ESD per IEC 61000-4-2 (Air) | VESD | -25 |  | 25 | kV |  | 1 |
| ESD per IEC 61000-4-2 (Contact) | VESD | -25 |  | 25 | kV |  | 1 |
| Reverse Working Voltage (VP-VN) | VRWM |  |  | 5.5 | V |  | 2 |
| Breakdown Voltage | VBR | 6 |  |  | V | IT=1mA, any I/O pin to ground | 2 |
| Junction capacitance (between I/O pins) | CJ |  | 0.35 |  | pF | VR=0V, f=1MHz, between I/O pins | 2 |

## CAD (KiCad official)

- Symbol: `CM1213A-04SO`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `cm1213a-04so-etched.step` / `cm1213a-04so-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cm1213a-04so.step` / `cm1213a-04so.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [UMW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8755876269315764224) (6 pp, sha256 `e481409719beb94f`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cm1213a-04so-datasheet.pdf)