component
CM1055-DS
Public Made by Adomby adom
iCM(创芯微) , SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CM1055-DS
iCM(创芯微) · IC · SOP-16
CM1055-DS from iCM(创芯微), in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Positive supply input and positive connection of battery 1; operating voltage is 5 to 25 V and the absolute maximum rating is VSS-0.3 to VSS+40 V. |
| 2 | VC1 | power_in | Positive voltage connection of battery 1 for cell voltage sensing; the cell input absolute maximum rating is 0 to 12 V. |
| 3 | VC2 | power_in | Negative voltage connection of battery 1 and positive voltage connection of battery 2 for cell voltage sensing; the cell input absolute maximum rating is 0 to 12 V. |
| 4 | VC3 | power_in | Negative voltage of battery 2 and positive voltage connection of battery 3 for cell voltage sensing; the cell input absolute maximum rating is 0 to 12 V. |
| 5 | VC4 | power_in | Negative voltage of battery 3 and positive voltage connection of battery 4 for cell voltage sensing; the cell input absolute maximum rating is 0 to 12 V. |
| 6 | VC5 | power_in | Negative voltage of battery 4 and positive voltage connection of battery 5 for cell voltage sensing; the cell input absolute maximum rating is 0 to 12 V. |
| 7 | VSS | power_in | Chip ground and negative voltage connection of battery 5; it is the reference for all absolute maximum voltage ratings. |
| 8 | NC | unconnected | No-connect pin with no electrical connection function. |
| 9 | TEC | passive | Discharge overcurrent delay adjustment terminal; the delay is set by external capacitor CTEC (TEC1 = 10 × CTEC, with TEC1 in ms and CTEC in nF), and the absolute maximum rating is VSS-0.3 to VSS+5.5 V. |
| 10 | RTS | input | Connects the NTC thermistor (B value 3950, 100 kΩ at 25 °C) for temperature detection; the absolute maximum rating is VSS-0.3 to VSS+5.5 V. |
| 11 | RTV | passive | Connects a resistor to the RTS pin to set the high-temperature protection threshold, with the resistor equal to 3 times the NTC resistance at the required TCH; the absolute maximum rating is VSS-0.3 to VSS+5.5 V. |
| 12 | VINI | input | Overcurrent detection input whose voltage rises with discharge current; the absolute maximum rating is VSS-0.3 to VCC+0.3 V. |
| 13 | DO | output | Discharge MOSFET control output, with high level VCC-0.7 V typical when VCC is below 12 V (10.8 V typical when VCC is above 12 V) and low level at VSS; the absolute maximum rating is VSS-0.3 to VCC+0.3 V. |
| 14 | CO | output | Charge NMOS control output, with high level VCC-0.7 V typical when VCC is below 12 V (10.8 V typical when VCC is above 12 V) and low level at VSS; the absolute maximum rating is VSS-15 to VCC+0.3 V. |
| 15 | VM | input | Charger and load detection terminal with about 70 kΩ typical resistance to VSS; the absolute maximum rating is VSS-15 to VCC+0.3 V. |
| 16 | COP | output | Charge PMOS control output, with high level VCC-0.7 V typical when VCC is below 12 V and low level at VSS; the absolute maximum rating is VSS-15 to VCC+0.3 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | iCM(创芯微) |
| Package | SOP-16 |
| Category | |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating voltage (VCC) | VCC | 5 | 25 | V | 6 | ||
| Normal operating current | IVCC | 12 | 18 | μA | V1=V2=V3=V4=V5=3.5V | 6 | |
| Sleep current | ISTB | 4 | 6 | μA | V1=V2=V3=V4=V5=2.0V | 6 | |
| Overcharge protection delay | TOC | 0.5 | 1 | 1.5 | s | V1=V2=V3=V4=V5=3.5V, V5=3.5 → 4.4V | 6 |
| Overcharge recovery delay | TOCR | 128 | 256 | 384 | ms | V1=V2=V3=V4=V5=3.5V, V5=4.4 → 3.5V | 6 |
| Overdischarge release voltage | VODR | -0.1 | 3 | 0.1 | V | V1=V2=V3=V4=V5=3.5V, V5=2.0 → 3.5V | 6 |
| Overdischarge protection delay | TOD | 0.5 | 1 | 1.5 | s | V1=V2=V3=V4=V5=3.5V, V5=3.5 → 2.0V | 6 |
| Overdischarge recovery delay | TODR | 24 | 48 | 72 | ms | V1=V2=V3=V4=V5=3.5V, V5=2.0 → 3.5V | 6 |
| Discharge overcurrent 1 protection voltage | VEC1 | -0.01 | 0.1 | 0.01 | V | V1=V2=V3=V4=V5=3.5V, VINI=0 → 0.12V | 6 |
| Discharge overcurrent 1 protection delay | TEC1 | 0.5 | 1 | 1.5 | s | V1=V2=V3=V4=V5=3.5V, VINI=0 → 0.12V, CTEC=0.1μF | 6 |
| Discharge overcurrent 2 protection delay | TEC2 | 50 | 100 | 150 | ms | V1=V2=V3=V4=V5=3.5V, VINI=0 → 0.35V | 6 |
| Short-circuit protection delay | TSHORT | 125 | 250 | 375 | μs | V1=V2=V3=V4=V5=3.5V, VINI=0 → 0.8V | 6 |
| Discharge overcurrent release delay | TECR | 16 | 32 | 48 | ms | V1=V2=V3=V4=V5=3.5V, VINI=0.8 → 0V | 6 |
| Charge overcurrent protection voltage | VCHA | -0.01 | -0.05 | 0.01 | V | V1=V2=V3=V4=V5=3.5V, VINI=0→ -1V | 6 |
| Charge overcurrent protection delay | TCHA | 128 | 256 | 384 | ms | V1=V2=V3=V4=V5=3.5V, VINI=0→ -1V | 7 |
| Charge overcurrent release delay | TCHAR | 24 | 48 | 72 | ms | V1=V2=V3=V4=V5=3.5V, VINI=-1V→0V | 7 |
| Wire-break protection delay | TOW | 260 | 520 | 780 | ms | 7 | |
| Wire-break release delay | TOWR | 24 | 48 | 72 | ms | 7 | |
| Charge high-temperature protection temperature tolerance | TCH | -5 | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 10k | 7 | |
| Charge high-temperature release temperature tolerance | TCHR | -5 | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=10k → 100k | 7 | |
| Discharge high-temperature protection temperature tolerance | TDH | -5 | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 10k | 7 | |
| Discharge high-temperature release temperature tolerance | TDHR | -5 | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=10k → 100k | 7 | |
| Charge high-temperature protection delay | DTCH | 0.5 | 1 | 1.5 | s | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 10k | 7 |
| Charge high-temperature release delay | DTCHR | 128 | 256 | 384 | ms | V1=V2=V3=V4=V5=3.5V, RNTC=10k → 100k | 7 |
| Discharge high-temperature protection delay | DTDH | 0.5 | 1 | 1.5 | s | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 10k | 7 |
| Discharge high-temperature release delay | DTDHR | 128 | 256 | 384 | ms | V1=V2=V3=V4=V5=3.5V, RNTC=10k → 100k | 7 |
| Charge low-temperature protection temperature tolerance | TCL | -5 | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 3M | 7 | |
| Charge low-temperature release temperature tolerance | TCLR | -5 | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=3M → 100k | 7 | |
| Discharge low-temperature protection temperature tolerance | TDL | -5 | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 3M | 7 | |
| Discharge low-temperature release temperature tolerance | TDLR | -5 | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=3M → 100k | 7 | |
| Charge low-temperature protection delay | DTCL | 0.7 | 1 | 1.3 | s | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 3M | 7 |
| Charge low-temperature release delay | DTCLR | 128 | 256 | 384 | ms | V1=V2=V3=V4=V5=3.5V, RNTC=3M → 100k | 7 |
| Discharge low-temperature protection delay | DTDL | 0.7 | 1 | 1.3 | s | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 3M | 7 |
| Discharge low-temperature release delay | DTDLR | 128 | 256 | 384 | ms | V1=V2=V3=V4=V5=3.5V, RNTC=3M → 100k | 7 |
| Discharge state detection voltage | VSTS | 1 | 4 | 7 | mV | V1=V2=V3=V4=V5=3.5V, RNTC=10k, VINI=0→10mV | 7 |
| Supply voltage (absolute maximum, referenced to VSS) | VCC | -0.3 | 40 | V | Referenced to VSS (VSS-0.3 ~ VSS+40) | 5 | |
| Input voltage between cell terminals | VCELL | 0 | 12 | V | VC5-VSS, VC4-VC5, VC3-VC4, VC2-VC3, VC1-VC2 | 5 | |
| Input voltage 1 (RTS, RTV, TEC) | VIN1 | -0.3 | 5.5 | V | Referenced to VSS (VSS-0.3 ~ VSS+5.5) for RTS, RTV, TEC | 5 | |
| Input voltage 2 (VM, COP, CO) | VIN2 | -15 | 0.3 | V | Min referenced to VSS (VSS-15), max referenced to VCC (VCC+0.3) | 5 | |
| Input voltage 3 (VINI, DO) | VIN3 | -0.3 | 0.3 | V | Min referenced to VSS (VSS-0.3), max referenced to VCC (VCC+0.3) | 5 | |
| Operating ambient temperature | TOPR | -40 | 85 | °C | 5 | ||
| Storage temperature | TSTG | -55 | 125 | °C | 5 |
CAD (KiCad official)
- Symbol:
CM1055-DS - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cm1055-ds-etched.step/cm1055-ds-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cm1055-ds.step/cm1055-ds.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: iCM(创芯微) datasheet (17 pp, sha256
eb9679a6544ef0d6, retrieved 2026-11-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CM1055-DS
**iCM(创芯微)** · IC · SOP-16
CM1055-DS from iCM(创芯微), in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Positive supply input and positive connection of battery 1; operating voltage is 5 to 25 V and the absolute maximum rating is VSS-0.3 to VSS+40 V. |
| 2 | VC1 | power_in | Positive voltage connection of battery 1 for cell voltage sensing; the cell input absolute maximum rating is 0 to 12 V. |
| 3 | VC2 | power_in | Negative voltage connection of battery 1 and positive voltage connection of battery 2 for cell voltage sensing; the cell input absolute maximum rating is 0 to 12 V. |
| 4 | VC3 | power_in | Negative voltage of battery 2 and positive voltage connection of battery 3 for cell voltage sensing; the cell input absolute maximum rating is 0 to 12 V. |
| 5 | VC4 | power_in | Negative voltage of battery 3 and positive voltage connection of battery 4 for cell voltage sensing; the cell input absolute maximum rating is 0 to 12 V. |
| 6 | VC5 | power_in | Negative voltage of battery 4 and positive voltage connection of battery 5 for cell voltage sensing; the cell input absolute maximum rating is 0 to 12 V. |
| 7 | VSS | power_in | Chip ground and negative voltage connection of battery 5; it is the reference for all absolute maximum voltage ratings. |
| 8 | NC | unconnected | No-connect pin with no electrical connection function. |
| 9 | TEC | passive | Discharge overcurrent delay adjustment terminal; the delay is set by external capacitor CTEC (TEC1 = 10 × CTEC, with TEC1 in ms and CTEC in nF), and the absolute maximum rating is VSS-0.3 to VSS+5.5 V. |
| 10 | RTS | input | Connects the NTC thermistor (B value 3950, 100 kΩ at 25 °C) for temperature detection; the absolute maximum rating is VSS-0.3 to VSS+5.5 V. |
| 11 | RTV | passive | Connects a resistor to the RTS pin to set the high-temperature protection threshold, with the resistor equal to 3 times the NTC resistance at the required TCH; the absolute maximum rating is VSS-0.3 to VSS+5.5 V. |
| 12 | VINI | input | Overcurrent detection input whose voltage rises with discharge current; the absolute maximum rating is VSS-0.3 to VCC+0.3 V. |
| 13 | DO | output | Discharge MOSFET control output, with high level VCC-0.7 V typical when VCC is below 12 V (10.8 V typical when VCC is above 12 V) and low level at VSS; the absolute maximum rating is VSS-0.3 to VCC+0.3 V. |
| 14 | CO | output | Charge NMOS control output, with high level VCC-0.7 V typical when VCC is below 12 V (10.8 V typical when VCC is above 12 V) and low level at VSS; the absolute maximum rating is VSS-15 to VCC+0.3 V. |
| 15 | VM | input | Charger and load detection terminal with about 70 kΩ typical resistance to VSS; the absolute maximum rating is VSS-15 to VCC+0.3 V. |
| 16 | COP | output | Charge PMOS control output, with high level VCC-0.7 V typical when VCC is below 12 V and low level at VSS; the absolute maximum rating is VSS-15 to VCC+0.3 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | iCM(创芯微) |
| Package | SOP-16 |
| Category | |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating voltage (VCC) | VCC | 5 | | 25 | V | | 6 |
| Normal operating current | IVCC | | 12 | 18 | μA | V1=V2=V3=V4=V5=3.5V | 6 |
| Sleep current | ISTB | | 4 | 6 | μA | V1=V2=V3=V4=V5=2.0V | 6 |
| Overcharge protection delay | TOC | 0.5 | 1 | 1.5 | s | V1=V2=V3=V4=V5=3.5V, V5=3.5 → 4.4V | 6 |
| Overcharge recovery delay | TOCR | 128 | 256 | 384 | ms | V1=V2=V3=V4=V5=3.5V, V5=4.4 → 3.5V | 6 |
| Overdischarge release voltage | VODR | -0.1 | 3 | 0.1 | V | V1=V2=V3=V4=V5=3.5V, V5=2.0 → 3.5V | 6 |
| Overdischarge protection delay | TOD | 0.5 | 1 | 1.5 | s | V1=V2=V3=V4=V5=3.5V, V5=3.5 → 2.0V | 6 |
| Overdischarge recovery delay | TODR | 24 | 48 | 72 | ms | V1=V2=V3=V4=V5=3.5V, V5=2.0 → 3.5V | 6 |
| Discharge overcurrent 1 protection voltage | VEC1 | -0.01 | 0.1 | 0.01 | V | V1=V2=V3=V4=V5=3.5V, VINI=0 → 0.12V | 6 |
| Discharge overcurrent 1 protection delay | TEC1 | 0.5 | 1 | 1.5 | s | V1=V2=V3=V4=V5=3.5V, VINI=0 → 0.12V, CTEC=0.1μF | 6 |
| Discharge overcurrent 2 protection delay | TEC2 | 50 | 100 | 150 | ms | V1=V2=V3=V4=V5=3.5V, VINI=0 → 0.35V | 6 |
| Short-circuit protection delay | TSHORT | 125 | 250 | 375 | μs | V1=V2=V3=V4=V5=3.5V, VINI=0 → 0.8V | 6 |
| Discharge overcurrent release delay | TECR | 16 | 32 | 48 | ms | V1=V2=V3=V4=V5=3.5V, VINI=0.8 → 0V | 6 |
| Charge overcurrent protection voltage | VCHA | -0.01 | -0.05 | 0.01 | V | V1=V2=V3=V4=V5=3.5V, VINI=0→ -1V | 6 |
| Charge overcurrent protection delay | TCHA | 128 | 256 | 384 | ms | V1=V2=V3=V4=V5=3.5V, VINI=0→ -1V | 7 |
| Charge overcurrent release delay | TCHAR | 24 | 48 | 72 | ms | V1=V2=V3=V4=V5=3.5V, VINI=-1V→0V | 7 |
| Wire-break protection delay | TOW | 260 | 520 | 780 | ms | | 7 |
| Wire-break release delay | TOWR | 24 | 48 | 72 | ms | | 7 |
| Charge high-temperature protection temperature tolerance | TCH | -5 | | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 10k | 7 |
| Charge high-temperature release temperature tolerance | TCHR | -5 | | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=10k → 100k | 7 |
| Discharge high-temperature protection temperature tolerance | TDH | -5 | | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 10k | 7 |
| Discharge high-temperature release temperature tolerance | TDHR | -5 | | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=10k → 100k | 7 |
| Charge high-temperature protection delay | DTCH | 0.5 | 1 | 1.5 | s | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 10k | 7 |
| Charge high-temperature release delay | DTCHR | 128 | 256 | 384 | ms | V1=V2=V3=V4=V5=3.5V, RNTC=10k → 100k | 7 |
| Discharge high-temperature protection delay | DTDH | 0.5 | 1 | 1.5 | s | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 10k | 7 |
| Discharge high-temperature release delay | DTDHR | 128 | 256 | 384 | ms | V1=V2=V3=V4=V5=3.5V, RNTC=10k → 100k | 7 |
| Charge low-temperature protection temperature tolerance | TCL | -5 | | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 3M | 7 |
| Charge low-temperature release temperature tolerance | TCLR | -5 | | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=3M → 100k | 7 |
| Discharge low-temperature protection temperature tolerance | TDL | -5 | | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 3M | 7 |
| Discharge low-temperature release temperature tolerance | TDLR | -5 | | 5 | °C | V1=V2=V3=V4=V5=3.5V, RNTC=3M → 100k | 7 |
| Charge low-temperature protection delay | DTCL | 0.7 | 1 | 1.3 | s | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 3M | 7 |
| Charge low-temperature release delay | DTCLR | 128 | 256 | 384 | ms | V1=V2=V3=V4=V5=3.5V, RNTC=3M → 100k | 7 |
| Discharge low-temperature protection delay | DTDL | 0.7 | 1 | 1.3 | s | V1=V2=V3=V4=V5=3.5V, RNTC=100k → 3M | 7 |
| Discharge low-temperature release delay | DTDLR | 128 | 256 | 384 | ms | V1=V2=V3=V4=V5=3.5V, RNTC=3M → 100k | 7 |
| Discharge state detection voltage | VSTS | 1 | 4 | 7 | mV | V1=V2=V3=V4=V5=3.5V, RNTC=10k, VINI=0→10mV | 7 |
| Supply voltage (absolute maximum, referenced to VSS) | VCC | -0.3 | | 40 | V | Referenced to VSS (VSS-0.3 ~ VSS+40) | 5 |
| Input voltage between cell terminals | VCELL | 0 | | 12 | V | VC5-VSS, VC4-VC5, VC3-VC4, VC2-VC3, VC1-VC2 | 5 |
| Input voltage 1 (RTS, RTV, TEC) | VIN1 | -0.3 | | 5.5 | V | Referenced to VSS (VSS-0.3 ~ VSS+5.5) for RTS, RTV, TEC | 5 |
| Input voltage 2 (VM, COP, CO) | VIN2 | -15 | | 0.3 | V | Min referenced to VSS (VSS-15), max referenced to VCC (VCC+0.3) | 5 |
| Input voltage 3 (VINI, DO) | VIN3 | -0.3 | | 0.3 | V | Min referenced to VSS (VSS-0.3), max referenced to VCC (VCC+0.3) | 5 |
| Operating ambient temperature | TOPR | -40 | | 85 | °C | | 5 |
| Storage temperature | TSTG | -55 | | 125 | °C | | 5 |
## CAD (KiCad official)
- Symbol: `CM1055-DS`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `cm1055-ds-etched.step` / `cm1055-ds-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cm1055-ds.step` / `cm1055-ds.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [iCM(创芯微) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603349407169998848) (17 pp, sha256 `eb9679a6544ef0d6`, retrieved 2026-11-07, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cm1055-ds-datasheet.pdf)