component
CM1048-ET
Public Made by Adomby adom
iCM(创芯微) Battery Management, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
CM1048-ET
iCM(创芯微) · Battery Management · TSSOP-16
CM1048-ET from iCM(创芯微), in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Positive power supply input and positive voltage connection for battery 4; absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 2 | VC4 | power_in | Positive voltage connection for battery 4; cell input absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 3 | VC4 | power_in | Positive voltage connection for battery 4 (second VC4 pin on the package); cell input absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 4 | VC3 | power_in | Connection for the negative terminal of battery 4 and the positive terminal of battery 3; cell input absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 5 | VC2 | power_in | Connection for the negative terminal of battery 3 and the positive terminal of battery 2; cell input absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 6 | VC1 | power_in | Connection for the negative terminal of battery 2 and the positive terminal of battery 1; cell input absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 7 | VSS | power_in | IC ground and negative terminal connection of battery 1; the reference for all voltage ratings in the datasheet. |
| 8 | SEL | input | Series-count select terminal for 3-series or 4-series operation; absolute maximum rating is VSS-0.3 V to VSS+5.0 V. |
| 9 | TEC | passive | Discharge overcurrent delay adjustment terminal where external capacitor CTEC sets TEC1 = 10×CTEC (nF) ms; absolute maximum rating is VSS-0.3 V to VSS+5.0 V. |
| 10 | CLR | passive | Connects a resistor to the NTC to set the charge low-temperature protection point; absolute maximum rating is VSS-0.3 V to VSS+5.0 V, and it may be left floating if temperature protection is not used. |
| 11 | DHR | passive | Connects a resistor to the NTC to set the discharge high-temperature protection point; absolute maximum rating is VSS-0.3 V to VSS+5.0 V. |
| 12 | CHR | passive | Connects a resistor to the NTC to set the charge high-temperature protection point; absolute maximum rating is VSS-0.3 V to VSS+5.0 V. |
| 13 | VINI | input | Overcurrent detection input for charge and discharge current sensing; absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 14 | DO | output | Discharge MOS control output that turns off the discharge MOSFET on protection; absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 15 | CO | output | Charge MOS control output that turns off the charge MOSFET on protection; absolute maximum rating is VSS-30 V to VSS+30 V. |
| 16 | VM | passive | Charger and load detection terminal; absolute maximum rating is VSS-30 V to VSS+30 V, with VM-VSS resistance RVMS typically 80 kΩ. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | iCM(创芯微) |
| Package | TSSOP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Overcharge protection delay | TOC | 0.7 | 1 | 1.3 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5→4.4V | 7 |
| Overcharge release delay | TOCR | 180 | 256 | 332 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=4.4→3.5V | 7 |
| Overdischarge release voltage (25 C) | VODR | -0.08 | 3 | 0.08 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=2.0→3.5V | 7 |
| Overdischarge protection delay | TOD | 0.7 | 1 | 1.3 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5→2.0V | 7 |
| Overdischarge release delay | TODR | 179 | 256 | 333 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=2.0→3.5V | 7 |
| Low-voltage charge inhibit voltage | VLV | 1.125 | 1.5 | 1.875 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5→1.2V | 7 |
| Low-voltage charge inhibit release voltage | VLVR | 1.1 | 1.52 | 1.94 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=1.2→3.5V | 7 |
| Low-voltage charge inhibit delay | TLV | 1 | 1.5 | 2 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5→1.2V | 7 |
| Discharge overcurrent 1 protection voltage (25 C) | VEC1 | -0.005 | 0.05 | 0.005 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→0.18V | 7 |
| Discharge overcurrent 1 protection delay | TEC1 | 0.7 | 1 | 1.3 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→0.18V, CTEC=0.1μF (±1%) | 7 |
| Discharge overcurrent 2 protection voltage (25 C) | VEC2 | -0.01 | 0.1 | 0.01 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→0.35V | 7 |
| Discharge overcurrent 2 protection delay | TEC2 | 70 | 100 | 130 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→0.35V, CTEC=0.1μF (±1%) | 7 |
| Short-circuit protection delay | TSHORT | 150 | 250 | 350 | μs | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→0.8V | 7 |
| Discharge overcurrent release delay | TECR | 22 | 32 | 42 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0.8→0V | 7 |
| Charge overcurrent protection delay | TCHA | 180 | 256 | 332 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→-1.0V | 8 |
| Charge overcurrent release delay | TCHAR | 45 | 64 | 83 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=-1V→0V | 8 |
| Charge high-temperature protection temperature (25 C) | TCH | -3 | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→1k | 8 | |
| Charge high-temperature release temperature (25 C) | TCHR | -3 | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=1k→10k | 8 | |
| Discharge high-temperature protection temperature (25 C) | TDH | -3 | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→1k | 8 | |
| Discharge high-temperature release temperature (25 C) | TDHR | -3 | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=1k→10k | 8 | |
| Charge high-temperature protection delay | DTCH | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→1k | 8 |
| Charge high-temperature release delay | DTCHR | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=1k→10k | 8 |
| Discharge high-temperature protection delay | DTDH | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→1k | 8 |
| Discharge high-temperature release delay | DTDHR | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=1k→10k | 8 |
| Charge low-temperature protection temperature (25 C) | TCL | -3 | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→3M | 8 | |
| Charge low-temperature release temperature (25 C) | TCLR | -3 | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=3M→10k | 8 | |
| Discharge low-temperature protection temperature (25 C) | TDL | -3 | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→3M | 8 | |
| Discharge low-temperature release temperature (25 C) | TDLR | -3 | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=3M→10k | 8 | |
| Charge low-temperature protection delay | DTCL | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→3M | 8 |
| Charge low-temperature release delay | DTCLR | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=3M→10k | 8 |
| Discharge low-temperature protection delay | DTDL | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→3M | 8 |
| Discharge low-temperature release delay | DTDLR | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=3M→10k | 8 |
| Discharge state detection voltage | VSTS | 1 | 4 | 7 | mV | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→10mV | 9 |
| Discharge state detection delay | TSTS | 3 | 4.5 | 6 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→10mV | 9 |
| Sleep delay | TSLP | 22 | 32 | 42 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5→1.5V | 9 |
| Normal operating current (-40 to +85 C) | IVCC | 10 | 18 | μA | Ta=-40~+85°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V | 10 | |
| Overdischarge release voltage (-40 to +85 C) | VODR | -0.1 | 3 | 0.1 | V | Ta=-40~+85°C; VCn-VCn+1=3.5V, VC1-VSS=2.0→3.5V | 10 |
| Low-voltage charge inhibit voltage (-40 to +85 C) | VLV | 1 | 1.5 | 2 | V | Ta=-40~+85°C; VCn-VCn+1=3.5V, VC1-VSS=3.5→1.2V | 10 |
| Low-voltage charge inhibit release voltage (-40 to +85 C) | VLVR | 0.99 | 1.52 | 2.05 | V | Ta=-40~+85°C; VCn-VCn+1=3.5V, VC1-VSS=1.2→3.5V | 10 |
| Discharge overcurrent 2 protection voltage (-40 to +85 C) | VEC2 | -0.02 | 0.1 | 0.02 | V | Ta=-40~+85°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→0.35V | 10 |
| Charge high-temperature protection temperature (-40 to +85 C) | TCH | -5 | 5 | °C | Ta=-40~+85°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→1k | 11 | |
| Supply voltage VCC (absolute maximum) | VCC | -0.3 | 30 | V | Ta=+25°C; relative to VSS (VSS-0.3~VSS+30) | 6 | |
| Cell input voltage VCn, n=1~4 (absolute maximum) | VCELL | -0.3 | 30 | V | Ta=+25°C; relative to VSS (VSS-0.3~VSS+30) | 6 | |
| Input voltage on SEL, TEC, CLR, DHR, CHR (absolute maximum) | VIN1 | -0.3 | 5 | V | Ta=+25°C; relative to VSS (VSS-0.3~VSS+5.0) | 6 | |
| Input voltage on VM, CO (absolute maximum) | VIN2 | -30 | 30 | V | Ta=+25°C; relative to VSS (VSS-30~VSS+30) | 6 | |
| Input voltage on DO, VINI (absolute maximum) | VIN3 | -0.3 | 30 | V | Ta=+25°C; relative to VSS (VSS-0.3~VSS+30) | 6 | |
| Operating ambient temperature | TOPR | -40 | 85 | °C | 6 | ||
| Storage temperature range | TSTG | -55 | 125 | °C | 6 |
CAD (KiCad official)
- Symbol:
CM1048-ET - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cm1048-et-etched.step/cm1048-et-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cm1048-et.step/cm1048-et.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: iCM(创芯微) datasheet (21 pp, sha256
4f7094f487e54c2d, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CM1048-ET
**iCM(创芯微)** · Battery Management · TSSOP-16
CM1048-ET from iCM(创芯微), in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Positive power supply input and positive voltage connection for battery 4; absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 2 | VC4 | power_in | Positive voltage connection for battery 4; cell input absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 3 | VC4 | power_in | Positive voltage connection for battery 4 (second VC4 pin on the package); cell input absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 4 | VC3 | power_in | Connection for the negative terminal of battery 4 and the positive terminal of battery 3; cell input absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 5 | VC2 | power_in | Connection for the negative terminal of battery 3 and the positive terminal of battery 2; cell input absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 6 | VC1 | power_in | Connection for the negative terminal of battery 2 and the positive terminal of battery 1; cell input absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 7 | VSS | power_in | IC ground and negative terminal connection of battery 1; the reference for all voltage ratings in the datasheet. |
| 8 | SEL | input | Series-count select terminal for 3-series or 4-series operation; absolute maximum rating is VSS-0.3 V to VSS+5.0 V. |
| 9 | TEC | passive | Discharge overcurrent delay adjustment terminal where external capacitor CTEC sets TEC1 = 10×CTEC (nF) ms; absolute maximum rating is VSS-0.3 V to VSS+5.0 V. |
| 10 | CLR | passive | Connects a resistor to the NTC to set the charge low-temperature protection point; absolute maximum rating is VSS-0.3 V to VSS+5.0 V, and it may be left floating if temperature protection is not used. |
| 11 | DHR | passive | Connects a resistor to the NTC to set the discharge high-temperature protection point; absolute maximum rating is VSS-0.3 V to VSS+5.0 V. |
| 12 | CHR | passive | Connects a resistor to the NTC to set the charge high-temperature protection point; absolute maximum rating is VSS-0.3 V to VSS+5.0 V. |
| 13 | VINI | input | Overcurrent detection input for charge and discharge current sensing; absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 14 | DO | output | Discharge MOS control output that turns off the discharge MOSFET on protection; absolute maximum rating is VSS-0.3 V to VSS+30 V. |
| 15 | CO | output | Charge MOS control output that turns off the charge MOSFET on protection; absolute maximum rating is VSS-30 V to VSS+30 V. |
| 16 | VM | passive | Charger and load detection terminal; absolute maximum rating is VSS-30 V to VSS+30 V, with VM-VSS resistance RVMS typically 80 kΩ. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | iCM(创芯微) |
| Package | TSSOP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Overcharge protection delay | TOC | 0.7 | 1 | 1.3 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5→4.4V | 7 |
| Overcharge release delay | TOCR | 180 | 256 | 332 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=4.4→3.5V | 7 |
| Overdischarge release voltage (25 C) | VODR | -0.08 | 3 | 0.08 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=2.0→3.5V | 7 |
| Overdischarge protection delay | TOD | 0.7 | 1 | 1.3 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5→2.0V | 7 |
| Overdischarge release delay | TODR | 179 | 256 | 333 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=2.0→3.5V | 7 |
| Low-voltage charge inhibit voltage | VLV | 1.125 | 1.5 | 1.875 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5→1.2V | 7 |
| Low-voltage charge inhibit release voltage | VLVR | 1.1 | 1.52 | 1.94 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=1.2→3.5V | 7 |
| Low-voltage charge inhibit delay | TLV | 1 | 1.5 | 2 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5→1.2V | 7 |
| Discharge overcurrent 1 protection voltage (25 C) | VEC1 | -0.005 | 0.05 | 0.005 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→0.18V | 7 |
| Discharge overcurrent 1 protection delay | TEC1 | 0.7 | 1 | 1.3 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→0.18V, CTEC=0.1μF (±1%) | 7 |
| Discharge overcurrent 2 protection voltage (25 C) | VEC2 | -0.01 | 0.1 | 0.01 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→0.35V | 7 |
| Discharge overcurrent 2 protection delay | TEC2 | 70 | 100 | 130 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→0.35V, CTEC=0.1μF (±1%) | 7 |
| Short-circuit protection delay | TSHORT | 150 | 250 | 350 | μs | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→0.8V | 7 |
| Discharge overcurrent release delay | TECR | 22 | 32 | 42 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0.8→0V | 7 |
| Charge overcurrent protection delay | TCHA | 180 | 256 | 332 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→-1.0V | 8 |
| Charge overcurrent release delay | TCHAR | 45 | 64 | 83 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=-1V→0V | 8 |
| Charge high-temperature protection temperature (25 C) | TCH | -3 | | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→1k | 8 |
| Charge high-temperature release temperature (25 C) | TCHR | -3 | | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=1k→10k | 8 |
| Discharge high-temperature protection temperature (25 C) | TDH | -3 | | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→1k | 8 |
| Discharge high-temperature release temperature (25 C) | TDHR | -3 | | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=1k→10k | 8 |
| Charge high-temperature protection delay | DTCH | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→1k | 8 |
| Charge high-temperature release delay | DTCHR | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=1k→10k | 8 |
| Discharge high-temperature protection delay | DTDH | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→1k | 8 |
| Discharge high-temperature release delay | DTDHR | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=1k→10k | 8 |
| Charge low-temperature protection temperature (25 C) | TCL | -3 | | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→3M | 8 |
| Charge low-temperature release temperature (25 C) | TCLR | -3 | | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=3M→10k | 8 |
| Discharge low-temperature protection temperature (25 C) | TDL | -3 | | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→3M | 8 |
| Discharge low-temperature release temperature (25 C) | TDLR | -3 | | 3 | °C | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=3M→10k | 8 |
| Charge low-temperature protection delay | DTCL | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→3M | 8 |
| Charge low-temperature release delay | DTCLR | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=3M→10k | 8 |
| Discharge low-temperature protection delay | DTDL | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→3M | 8 |
| Discharge low-temperature release delay | DTDLR | 1.05 | 1.5 | 1.95 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=3M→10k | 8 |
| Discharge state detection voltage | VSTS | 1 | 4 | 7 | mV | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→10mV | 9 |
| Discharge state detection delay | TSTS | 3 | 4.5 | 6 | ms | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→10mV | 9 |
| Sleep delay | TSLP | 22 | 32 | 42 | s | Ta=+25°C; VCn-VCn+1=3.5V, VC1-VSS=3.5→1.5V | 9 |
| Normal operating current (-40 to +85 C) | IVCC | | 10 | 18 | μA | Ta=-40~+85°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V | 10 |
| Overdischarge release voltage (-40 to +85 C) | VODR | -0.1 | 3 | 0.1 | V | Ta=-40~+85°C; VCn-VCn+1=3.5V, VC1-VSS=2.0→3.5V | 10 |
| Low-voltage charge inhibit voltage (-40 to +85 C) | VLV | 1 | 1.5 | 2 | V | Ta=-40~+85°C; VCn-VCn+1=3.5V, VC1-VSS=3.5→1.2V | 10 |
| Low-voltage charge inhibit release voltage (-40 to +85 C) | VLVR | 0.99 | 1.52 | 2.05 | V | Ta=-40~+85°C; VCn-VCn+1=3.5V, VC1-VSS=1.2→3.5V | 10 |
| Discharge overcurrent 2 protection voltage (-40 to +85 C) | VEC2 | -0.02 | 0.1 | 0.02 | V | Ta=-40~+85°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, VINI=0→0.35V | 10 |
| Charge high-temperature protection temperature (-40 to +85 C) | TCH | -5 | | 5 | °C | Ta=-40~+85°C; VCn-VCn+1=3.5V, VC1-VSS=3.5V, RNTC=10k→1k | 11 |
| Supply voltage VCC (absolute maximum) | VCC | -0.3 | | 30 | V | Ta=+25°C; relative to VSS (VSS-0.3~VSS+30) | 6 |
| Cell input voltage VCn, n=1~4 (absolute maximum) | VCELL | -0.3 | | 30 | V | Ta=+25°C; relative to VSS (VSS-0.3~VSS+30) | 6 |
| Input voltage on SEL, TEC, CLR, DHR, CHR (absolute maximum) | VIN1 | -0.3 | | 5 | V | Ta=+25°C; relative to VSS (VSS-0.3~VSS+5.0) | 6 |
| Input voltage on VM, CO (absolute maximum) | VIN2 | -30 | | 30 | V | Ta=+25°C; relative to VSS (VSS-30~VSS+30) | 6 |
| Input voltage on DO, VINI (absolute maximum) | VIN3 | -0.3 | | 30 | V | Ta=+25°C; relative to VSS (VSS-0.3~VSS+30) | 6 |
| Operating ambient temperature | TOPR | -40 | | 85 | °C | | 6 |
| Storage temperature range | TSTG | -55 | | 125 | °C | | 6 |
## CAD (KiCad official)
- Symbol: `CM1048-ET`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `cm1048-et-etched.step` / `cm1048-et-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cm1048-et.step` / `cm1048-et.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [iCM(创芯微) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603349402606190592) (21 pp, sha256 `4f7094f487e54c2d`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cm1048-et-datasheet.pdf)