component
CLVC574AQPWRG4Q1
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 3d ago |
| viewers | 5d ago |
| clvc574aqpwrg4q1-etched.fit.json | 3d ago |
| clvc574aqpwrg4q1-etched.glb | 3d ago |
| clvc574aqpwrg4q1-etched.step | 3d ago |
| clvc574aqpwrg4q1.glb | 5d ago |
| clvc574aqpwrg4q1.kicad_mod | 5d ago |
| clvc574aqpwrg4q1.kicad_sym | 5d ago |
| clvc574aqpwrg4q1.lbr | 5d ago |
| clvc574aqpwrg4q1.step | 5d ago |
| package.json | 5d ago |
| page.json | 5d ago |
| README.md | 5d ago |
CLVC574AQPWRG4Q1
Texas Instruments · Flip Flops · TSSOP-20
CLVC574AQPWRG4Q1 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Output Enable input, active low; disables outputs to high-impedance when HIGH; VI = 0 to 5.5 V |
| 2 | 1D | input | Data input D1, latched on positive clock edge; VI = 0 to 5.5 V |
| 3 | 2D | input | Data input D2, latched on positive clock edge; VI = 0 to 5.5 V |
| 4 | 3D | input | Data input D3, latched on positive clock edge; VI = 0 to 5.5 V |
| 5 | 4D | input | Data input D4, latched on positive clock edge; VI = 0 to 5.5 V |
| 6 | 5D | input | Data input D5, latched on positive clock edge; VI = 0 to 5.5 V |
| 7 | 6D | input | Data input D6, latched on positive clock edge; VI = 0 to 5.5 V |
| 8 | 7D | input | Data input D7, latched on positive clock edge; VI = 0 to 5.5 V |
| 9 | 8D | input | Data input D8, latched on positive clock edge; VI = 0 to 5.5 V |
| 10 | GND | power_in | Ground, reference potential |
| 11 | CLK | input | Clock input, positive edge triggered; latches D inputs to Q outputs; VI = 0 to 5.5 V |
| 12 | 8Q | tri_state | Data output Q8, tri-state capable; VO = 0 to 5.5 V |
| 13 | 7Q | tri_state | Data output Q7, tri-state capable; VO = 0 to 5.5 V |
| 14 | 6Q | tri_state | Data output Q6, tri-state capable; VO = 0 to 5.5 V |
| 15 | 5Q | tri_state | Data output Q5, tri-state capable; VO = 0 to 5.5 V |
| 16 | 4Q | tri_state | Data output Q4, tri-state capable; VO = 0 to 5.5 V |
| 17 | 3Q | tri_state | Data output Q3, tri-state capable; VO = 0 to 5.5 V |
| 18 | 2Q | tri_state | Data output Q2, tri-state capable; VO = 0 to 5.5 V |
| 19 | 1Q | tri_state | Data output Q1, tri-state capable; VO = 0 to 5.5 V |
| 20 | VCC | power_in | Supply voltage, operating range 2 V to 3.6 V |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
CLVC574AQPWRG4Q1 - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
clvc574aqpwrg4q1-etched.step/clvc574aqpwrg4q1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);clvc574aqpwrg4q1.step/clvc574aqpwrg4q1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (16 pp, sha256
099aaf10d59c2630, retrieved 2026-09-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).