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CLRC66303HNY

Public Made by Adom

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NXP Semicon RF Chips, HVQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CLRC66303HNY

NXP Semicon · RF Chips · HVQFN-32-EP(5x5)

CLRC66303HNY from NXP Semicon, in a HVQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TDO / OUT0 output Test data output for the boundary scan interface, also usable as general purpose output 0.
2 TDI / OUT1 bidirectional Test data input for the boundary scan interface, also usable as general purpose output 1.
3 TMS / OUT2 bidirectional Test mode select for the boundary scan interface, also usable as general purpose output 2.
4 TCK / OUT3 bidirectional Test clock for the boundary scan interface, also usable as general purpose output 3.
5 SIGIN /OUT7 bidirectional Contactless communication interface output, also usable as general purpose output 7.
6 SIGOUT output Contactless communication interface input (the datasheet prints this pin as type O).
7 DVDD power_in Digital power supply buffer; used only for connection of a buffer capacitor, and connecting a supply voltage might damage the device.
8 VDD power_in Power supply, with the operating range given in the features as 2.5 V to 5.5 V for CLRC66303.
9 AVDD power_in Analog power supply buffer; used only for connection of a buffer capacitor, and connecting a supply voltage might damage the device.
10 AUX1 output Auxiliary output used for an analog test signal.
11 AUX2 output Auxiliary output used for an analog test signal.
12 RXP input Receiver input pin for the received RF signal.
13 RXN input Receiver input pin for the received RF signal.
14 VMID power_out Internal receiver reference voltage; used only for connection of a buffer capacitor, and connecting a supply voltage might damage the device.
15 TX2 output Transmitter 2 delivers the modulated 13.56 MHz carrier.
16 TVSS power_in Transmitter ground supplying the output stage of TX1 and TX2.
17 TX1 output Transmitter 1 delivers the modulated 13.56 MHz carrier.
18 TVDD power_in Transmitter voltage supply.
19 XTAL1 input Input to the inverting amplifier of the crystal oscillator; also the input for an externally generated clock (fosc = 27.12 MHz).
20 XTAL2 output Output of the inverting amplifier of the crystal oscillator.
21 PDOWN input Power down input that performs a reset.
22 CLKOUT / OUT6 output Clock output, also usable as general purpose output 6.
23 SCL output Serial clock line of the I2C interface (the datasheet prints this pin as type O).
24 SDA bidirectional Serial data line.
25 PVDD power_in Pad power supply.
26 IFSEL0 / OUT4 input Host interface selection 0, also usable as general purpose output 4.
27 IFSEL1 / OUT5 input Host interface selection 1, also usable as general purpose output 5.
28 IF0 bidirectional Multifunction interface pin that can be assigned to host interface RS232, SPI, I2C or I2C-L.
29 IF1 bidirectional Multifunction interface pin that can be assigned to host interface SPI, I2C or I2C-L.
30 IF2 bidirectional Multifunction interface pin that can be assigned to host interface RS232, SPI, I2C or I2C-L.
31 IF3 bidirectional Multifunction interface pin that can be assigned to host interface RS232, SPI, I2C or I2C-L.
32 IRQ output Interrupt request output that signals an interrupt event.
33 VSS power_in Ground and heat sink connection (central exposed pad).

Key specifications

Parameter Value
Manufacturer NXP Semicon
Package HVQFN-32-EP(5x5)
Category RF & Radio
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 6 V 115
PVDD supply voltage VDD(PVDD) -0.5 6 V 115
TVDD supply voltage VDD(TVDD) -0.5 6 V 115
TVDD supply current IDD(TVDD) 500 mA CLRC66303 115
input voltage on pin RXP Vi(RXP) -0.5 2 V 115
input voltage on pin RXN Vi(RXN) -0.5 2 V 115
total power dissipation per package Ptot 1125 mW 115
electrostatic discharge voltage VESD -2000 2000 V human body model (HBM), 1500 Ω, 100 pF 115
electrostatic discharge voltage VESD -500 500 V charge device model (CDM) 115
maximum junction temperature Tj(max) 150 °C 115
storage temperature Tstg -55 150 °C no supply voltage applied 115
supply voltage VDD 2.5 5 5.5 V 116
TVDD supply voltage VDD(TVDD) 2.5 5 5.5 V 116
PVDD supply voltage VDD(PVDD) 2.5 5 5.5 V all host interfaces except I2C interface 116
PVDD supply voltage VDD(PVDD) 3 5 5.5 V all host interfaces incl. I2C interface 116
maximum junction temperature Tj(max) 125 °C 116
operating ambient temperature Tamb -40 25 105 °C HVQFN32 package, in still air with exposed pin soldered on a 4 layer JEDEC PCB 116
storage temperature Tstg -45 25 125 °C no supply voltage applied, relative humidity 45...75% 116
thermal resistance from junction to ambient HVQFN32 Rth(j-a) 40 K/W in still air with exposed pin soldered on a 4 layer JEDEC PCB 117
supply current, modem on IDD 17 20 mA IDD = AVDD+DVDD; modem on (transmitter and receiver are switched on) 118
supply current, modem off IDD 0.45 0.5 mA IDD = AVDD+DVDD; modem off (transmitter and receiver are switched off) 118
PVDD supply current IDD(PVDD) 0.5 5 μA no load on digital pins, leakage current only 118
TVDD supply current IDD(TVDD) 250 350 mA CLRC66303HN 118
power-down current Ipd 40 400 nA All OUTx pins floating; ambient temp = +25 °C 118
power-down current Ipd 1.5 2.1 μA All OUTx pins floating; ambient temp = -40°C...+85°C 118
power-down current Ipd 3.5 5.2 μA All OUTx pins floating; CLRC66303: ambient temp = +105 °C 118
standby current Istby 3 6 μA All OUTx pins floating; ambient temp = 25 °C, IVDD+ITVDD+IPVDD 118
standby current Istby 5.25 26 μA All OUTx pins floating; ambient temp = -40°C...+105°C, Istby = IVDD+ITVDD+IPVDD 118
LPCD sleep current ILPCD(sleep) 3.3 6.3 μA All OUTx pins floating; LFO active, no RF field on, ambient temp = 25 °C 118
external buffer capacitor AVDD CL 220 470 nF 119
external buffer capacitor DVDD CL 220 470 nF 119
input leakage current ILI 0 50 500 nA output disabled 119
low-level input voltage VIL -0.5 V 119
low-level output voltage VOL 0 0 0.4 V 119
input capacitance Ci 0 2.5 4.5 pF 119
low-level input voltage PDOWN VIL 0 0 0.4 V 119
pull-up resistance Rpu 50 72 120 KΩ pins TCK, TMS, TDI, IF2 119
output voltage AUX 1, AUX 2 Vo 0 1.8 V 119
load capacitance AUX 1, AUX 2 CL 0 400 pF 119
input voltage RXP, RXN Vi(p) 0 1.65 1.8 V 119
input capacitance RXP, RXN Ci 2 3.5 5 pF 119
input voltage pin XTAL1 Vi 0 1.8 V pin XTAL1 120
equivalent series resistance ESR 50 100 Ω crystal requirements 120
crystal power dissipation Pxtal 50 100 μW crystal requirements 120
input leakage current IF3-SDA ILI 2 100 nA output disabled 120
low-level input voltage IF3-SDA VIL -0.5 V I2C configuration 120
low-level output voltage IF3-SDA VOL 0.3 V IOL = 3 mA 120
low-level output current IF3-SDA IOL 4 mA VOL = 0.4 V; Standard mode, Fast mode 120
low-level output current IF3-SDA IOL 6 mA VOL = 0.6 V; Standard mode, Fast mode 120
output fall time tf(o) 250 ns Standard mode, Fast mode, CL < 400 pF 120
output fall time tf(o) 120 ns Fast mode +; CL < 550 pF 120
pulse width of spikes suppressed by input filter tSP 0 50 ns 120
input capacitance IF3-SDA Ci 3.5 5 pF 120
load capacitance IF3-SDA CL 400 pF Standard mode 120
load capacitance IF3-SDA CL 550 pF Fast mode 120
EEPROM data retention time tEER 10 year Tamb = +55 °C 120

CAD (KiCad official)

  • Symbol: CLRC66303HNY
  • Footprint: Package_DFN_QFN:HVQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm
  • 3D model: HVQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: clrc66303hny-etched.step / clrc66303hny-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); clrc66303hny.step / clrc66303hny.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NXP Semicon datasheet (178 pp, sha256 f783e0576499744b, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF