# CLR6219SQA

**ChipLink Tech** · AC-DC Controllers & Regulators · SOP-8

CLR6219SQA from ChipLink Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground / MOSFET source return. Tie to secondary-side ground plane together with pins 2 and 3 for low-impedance return of the internal power MOSFET. |
| 2 | GND | power_in | Ground / MOSFET source return. Parallel with pins 1 and 3; also serves as source of the internal N-MOSFET. |
| 3 | GND | power_in | Ground / MOSFET source return. Parallel with pins 1 and 2 for current handling and thermal dissipation. |
| 4 | VDD | power_in | Chip supply pin. Recommended operating range 7-9 V; UVLO release ~3.85 V, UVLO fall ~3.6 V. Bypass with a 0.1 µF ceramic capacitor to GND. Typical operating current 56 µA at VDD = 6 V. |
| 5 | SW | power_out | Drain of the internal N-channel power MOSFET (BVdss = 40 V, Rds(on) = 19 mΩ typ at VGS = 4.5 V, IDS = 20 A). Also the VSW sense node used to trigger MOS on at VSW < -300 mV and off at VSW > -5 mV. Connect to the transformer secondary winding. |
| 6 | SW | power_out | Drain of the internal N-channel power MOSFET. Parallel with pins 5, 7, 8 for current and thermal handling. |
| 7 | SW | power_out | Drain of the internal N-channel power MOSFET. Parallel with pins 5, 6, 8. |
| 8 | SW | power_out | Drain of the internal N-channel power MOSFET. Parallel with pins 5, 6, 7. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ChipLink Tech |
| Package | SOP-8 |
| Category | Power Supply Chip |
| Pins | 8 |

## Ordering variants

Same part, different packaging or reel option.

- `CLR6219SQA`
- `CLR6218SQA`
- `CLR6220SQA`

## CAD (KiCad official)

- Symbol: `CLR6219SQA`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `clr6219sqa-etched.step` / `clr6219sqa-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `clr6219sqa.step` / `clr6219sqa.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ChipLink Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590233877110288384) (9 pp, sha256 `3a23b308c11560be`, retrieved 2026-08-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/clr6219sqa-datasheet.pdf)