component
CLM2543IDW
Public Made by Adomby adom
CHIPLON Analog To Digital Converters (ADCs), SOIC-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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CLM2543IDW
CHIPLON · Analog To Digital Converters (ADCs) · SOIC-20
CLM2543IDW from CHIPLON, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AIN0 | input | Analog input 0 of the 11 multiplexed analog inputs; for 4.1 MHz I/O CLOCK operation the source impedance must be 50 ohm or less and able to drive 60 pF. |
| 2 | AIN1 | input | Analog input 1 of the 11 multiplexed analog inputs; for 4.1 MHz I/O CLOCK operation the source impedance must be 50 ohm or less and able to drive 60 pF. |
| 3 | AIN2 | input | Analog input 2 of the 11 multiplexed analog inputs; for 4.1 MHz I/O CLOCK operation the source impedance must be 50 ohm or less and able to drive 60 pF. |
| 4 | AIN3 | input | Analog input 3 of the 11 multiplexed analog inputs; for 4.1 MHz I/O CLOCK operation the source impedance must be 50 ohm or less and able to drive 60 pF. |
| 5 | AIN4 | input | Analog input 4 of the 11 multiplexed analog inputs; for 4.1 MHz I/O CLOCK operation the source impedance must be 50 ohm or less and able to drive 60 pF. |
| 6 | AIN5 | input | Analog input 5 of the 11 multiplexed analog inputs; for 4.1 MHz I/O CLOCK operation the source impedance must be 50 ohm or less and able to drive 60 pF. |
| 7 | AIN6 | input | Analog input 6 of the 11 multiplexed analog inputs; for 4.1 MHz I/O CLOCK operation the source impedance must be 50 ohm or less and able to drive 60 pF. |
| 8 | AIN7 | input | Analog input 7 of the 11 multiplexed analog inputs; for 4.1 MHz I/O CLOCK operation the source impedance must be 50 ohm or less and able to drive 60 pF. |
| 9 | AIN8 | input | Analog input 8 of the 11 multiplexed analog inputs; for 4.1 MHz I/O CLOCK operation the source impedance must be 50 ohm or less and able to drive 60 pF. |
| 10 | GND | power_in | Ground return terminal for the internal circuitry; all voltage measurements are referenced to GND unless otherwise noted. |
| 11 | AIN9 | input | Analog input 9 of the 11 multiplexed analog inputs; for 4.1 MHz I/O CLOCK operation the source impedance must be 50 ohm or less and able to drive 60 pF. |
| 12 | AIN10 | input | Analog input 10 of the 11 multiplexed analog inputs; for 4.1 MHz I/O CLOCK operation the source impedance must be 50 ohm or less and able to drive 60 pF. |
| 13 | REF- | input | Negative reference voltage, the lower reference value (normally ground), which together with REF+ sets the maximum input voltage range. |
| 14 | REF+ | input | Positive reference voltage, the upper reference value (normally VCC); the maximum input range is set by the difference between the voltages on REF+ and REF-. |
| 15 | CS | input | Chip select; a high-to-low transition resets the internal counter and controls and enables DATA OUT, DATA INPUT and I/O CLOCK, and a low-to-high transition disables DATA INPUT and I/O CLOCK within the setup time. |
| 16 | DATA OUT | tri_state | Three-state serial output of the A/D conversion result that is high-impedance when CS is high and active when CS is low, shifting out the previous result MSB/LSB first, with data changing on I/O CLOCK falling edges. |
| 17 | DATA INPUT | input | Serial data input whose 4-bit serial address, supplied MSB first, selects the analog input or test voltage to convert and is shifted in on the first four rising edges of I/O CLOCK. |
| 18 | I/O CLOCK | input | Input/output clock that shifts the 8 input data bits in on its first eight rising edges, shifts the previous conversion result out of DATA OUT, starts analog input sampling on the fourth falling edge, and hands control to the internal state controller on the last falling edge. |
| 19 | EOC | output | End-of-conversion output that goes from high to low after the last I/O CLOCK falling edge and stays low until the conversion is complete and data is ready for transfer. |
| 20 | VCC | power_in | Positive supply voltage, recommended 4.5 V to 5.5 V (absolute maximum -0.5 V to 6.5 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CHIPLON |
| Package | SOIC-20 |
| Category | ADC/DAC/Data Conversion |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
CLM2543IDW - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20 (KiCad packages3D, STEP)
- 3D model files:
clm2543idw-etched.step/clm2543idw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);clm2543idw.step/clm2543idw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CHIPLON datasheet (36 pp, sha256
c4eaa1a29bcf6331, retrieved 2026-11-02, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).