component
CL9975A50P3N
Public Made by Adomby adom
CHIPLINK(芯联) Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-89-3L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
CL9975A50P3N
CHIPLINK(芯联) · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-89-3L
CL9975A50P3N from CHIPLINK(芯联), in a SOT-89-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground terminal (接地端) of the regulator; the datasheet gives no further electrical limits for this pin. |
| 2 | VIN | power_in | Power supply input, with a maximum input voltage of 18 V; the input must stay at least Vout+1 V for the 150 mA test condition. |
| 3 | VOUT | power_out | Regulated output for this 5.0 V variant (CL9975A50P3N), rated up to 150 mA with ±2% output voltage accuracy and a typical dropout of 100 mV at 1 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CHIPLINK(芯联) |
| Package | SOT-89-3L |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Quiescent current | IQ | 2.5 | 3.5 | uA | 4 | ||
| Input voltage | VIN | 18 | V | 4 | |||
| Maximum output current | IOUT (max) | 150 | mA | VIN =Vout+1V | 4 | ||
| Load regulation | ∆VOUT | 60 | 150 | mV | VIN =Vout+2V, 1mA≤IOUT≤70mA | 4 | |
| Dropout voltage | Vdif1 | 100 | mV | IOUT =1mA | 4 | ||
| Output voltage temperature coefficient | ∆VOUT/∆Ta | -0.75 | 0.75 | mV/℃ | VDD=Vout+2V Iout=10mA 0℃＜Ta＜70℃ | 4 | |
| Line regulation | ∆VOUT/∆VIN * VOUT | 0.2 | %/V | IOUT =1mA, Vout+2V≤VIN≤18 | 4 | ||
| Output voltage | VOUT | 5 | V | VDD=Vout+2V Iout=10mA | 4 |
CAD (KiCad official)
- Symbol:
CL9975A50P3N - Footprint:
Package_TO_SOT_SMD:SOT-89-3 - 3D model: SOT-89-3L (KiCad packages3D, STEP)
- 3D model files:
cl9975a50p3n-etched.step/cl9975a50p3n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cl9975a50p3n.step/cl9975a50p3n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CHIPLINK(芯联) datasheet (8 pp, sha256
6c62ecc40b52235b, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CL9975A50P3N
**CHIPLINK(芯联)** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-89-3L
CL9975A50P3N from CHIPLINK(芯联), in a SOT-89-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground terminal (接地端) of the regulator; the datasheet gives no further electrical limits for this pin. |
| 2 | VIN | power_in | Power supply input, with a maximum input voltage of 18 V; the input must stay at least Vout+1 V for the 150 mA test condition. |
| 3 | VOUT | power_out | Regulated output for this 5.0 V variant (CL9975A50P3N), rated up to 150 mA with ±2% output voltage accuracy and a typical dropout of 100 mV at 1 mA. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CHIPLINK(芯联) |
| Package | SOT-89-3L |
| Category | Power Management (PMIC) |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Quiescent current | IQ | | 2.5 | 3.5 | uA | | 4 |
| Input voltage | VIN | | | 18 | V | | 4 |
| Maximum output current | IOUT (max) | 150 | | | mA | VIN =Vout+1V | 4 |
| Load regulation | ∆VOUT | | 60 | 150 | mV | VIN =Vout+2V, 1mA≤IOUT≤70mA | 4 |
| Dropout voltage | Vdif1 | | | 100 | mV | IOUT =1mA | 4 |
| Output voltage temperature coefficient | ∆VOUT/∆Ta | -0.75 | | 0.75 | mV/℃ | VDD=Vout+2V Iout=10mA 0℃＜Ta＜70℃ | 4 |
| Line regulation | ∆VOUT/∆VIN * VOUT | | 0.2 | | %/V | IOUT =1mA, Vout+2V≤VIN≤18 | 4 |
| Output voltage | VOUT | | 5 | | V | VDD=Vout+2V Iout=10mA | 4 |
## CAD (KiCad official)
- Symbol: `CL9975A50P3N`
- Footprint: `Package_TO_SOT_SMD:SOT-89-3`
- 3D model: SOT-89-3L (KiCad packages3D, STEP)
- 3D model files: `cl9975a50p3n-etched.step` / `cl9975a50p3n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cl9975a50p3n.step` / `cl9975a50p3n.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [CHIPLINK(芯联) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603127082281021440) (8 pp, sha256 `6c62ecc40b52235b`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cl9975a50p3n-datasheet.pdf)