component
CL9975A50L3N
Public Made by Adomby adom
CHIPLINK(芯联) Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CL9975A50L3N
CHIPLINK(芯联) · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L
CL9975A50L3N from CHIPLINK(芯联), in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | 接地端 (ground terminal) of the LDO; the datasheet gives no electrical limit for this pin. |
| 2 | VOUT | power_out | Regulated output terminal, rated for a maximum output current of 150 mA (Pd ≤ 250 mW) with output voltage accuracy of ±2%. |
| 3 | VIN | power_in | Power input terminal; the maximum input voltage is 18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CHIPLINK(芯联) |
| Package | SOT-23-3L |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 输入电压 (最大输入电压) | VIN | 18 | V | 4 | |||
| 最大输出电流 | IOUT (max) | 150 | mA | VIN =Vout+1V | 4 | ||
| 静态电流 | IQ | 2.5 | 3.5 | uA | 4 | ||
| 输出电压精度 | -2 | 2 | % | 1 | |||
| 负载特性 (负载调整率) | ΔVOUT | 60 | 150 | mV | VIN =Vout+2V, 1mA≤IOUT≤70mA | 4 | |
| 压差 | Vdif1 | 100 | mV | IOUT =1mA | 4 | ||
| 电源电压调整率 | ΔVOUT/ΔVIN*VOUT | 0.2 | %/V | IOUT =1mA, Vout+2V≤VIN≤18 | 4 | ||
| 输出电压温度系数 | ΔVOUT/ΔTa | -0.75 | 0.75 | mV/℃ | VDD=Vout+2V Iout=10mA 0℃＜Ta＜70℃ | 4 | |
| 人体模型ESD级别 (HBM) | 4000 | V | 3 | ||||
| 机器模型ESD级别 (MM) | 400 | V | 3 | ||||
| Latch-up 级别 | 400 | mA | 3 |
CAD (KiCad official)
- Symbol:
CL9975A50L3N - Footprint:
Package_TO_SOT_SMD:SOT-23-3 - 3D model: SOT-23-3L (KiCad packages3D, STEP)
- 3D model files:
cl9975a50l3n-etched.step/cl9975a50l3n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cl9975a50l3n.step/cl9975a50l3n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CHIPLINK(芯联) datasheet (8 pp, sha256
6c62ecc40b52235b, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CL9975A50L3N
**CHIPLINK(芯联)** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L
CL9975A50L3N from CHIPLINK(芯联), in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | 接地端 (ground terminal) of the LDO; the datasheet gives no electrical limit for this pin. |
| 2 | VOUT | power_out | Regulated output terminal, rated for a maximum output current of 150 mA (Pd ≤ 250 mW) with output voltage accuracy of ±2%. |
| 3 | VIN | power_in | Power input terminal; the maximum input voltage is 18 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CHIPLINK(芯联) |
| Package | SOT-23-3L |
| Category | Power Management (PMIC) |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 输入电压 (最大输入电压) | VIN | | | 18 | V | | 4 |
| 最大输出电流 | IOUT (max) | | | 150 | mA | VIN =Vout+1V | 4 |
| 静态电流 | IQ | | 2.5 | 3.5 | uA | | 4 |
| 输出电压精度 | | -2 | | 2 | % | | 1 |
| 负载特性 (负载调整率) | ΔVOUT | | 60 | 150 | mV | VIN =Vout+2V, 1mA≤IOUT≤70mA | 4 |
| 压差 | Vdif1 | | | 100 | mV | IOUT =1mA | 4 |
| 电源电压调整率 | ΔVOUT/ΔVIN*VOUT | | | 0.2 | %/V | IOUT =1mA, Vout+2V≤VIN≤18 | 4 |
| 输出电压温度系数 | ΔVOUT/ΔTa | -0.75 | | 0.75 | mV/℃ | VDD=Vout+2V Iout=10mA 0℃＜Ta＜70℃ | 4 |
| 人体模型ESD级别 (HBM) | | | | 4000 | V | | 3 |
| 机器模型ESD级别 (MM) | | | | 400 | V | | 3 |
| Latch-up 级别 | | | | 400 | mA | | 3 |
## CAD (KiCad official)
- Symbol: `CL9975A50L3N`
- Footprint: `Package_TO_SOT_SMD:SOT-23-3`
- 3D model: SOT-23-3L (KiCad packages3D, STEP)
- 3D model files: `cl9975a50l3n-etched.step` / `cl9975a50l3n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cl9975a50l3n.step` / `cl9975a50l3n.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [CHIPLINK(芯联) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590905792637706240) (8 pp, sha256 `6c62ecc40b52235b`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cl9975a50l3n-datasheet.pdf)