Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

CL9975A25L3N

CHIPLINK(芯联) · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L

CL9975A25L3N from CHIPLINK(芯联), in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground terminal of the LDO regulator (接地端).
2 VOUT power_out Regulated output; the output voltage is set by the part marking, with a family range of 1.2V to 5.0V in 0.1V steps and ±2% accuracy, and it sources up to 150mA (Pd≤250mW).
3 VIN power_in Power supply input (电源端); the maximum input voltage is 18V.

Key specifications

Parameter Value
Manufacturer CHIPLINK(芯联)
Package SOT-23-3L
Category Power Management (PMIC)
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage accuracy (VOUT tolerance) -2 2 % 1
Maximum output current IOUT (max) 150 mA VIN =Vout+1V 4
Load regulation ΔVOUT 60 150 mV VIN =Vout+2V, 1mA≤IOUT≤70mA 4
Input voltage VIN 18 V 4
Quiescent current IQ 2.5 3.5 uA 4
Dropout voltage Vdif1 100 mV IOUT =1mA 4
Line regulation ΔVOUT/(ΔVIN*VOUT) 0.2 %/V IOUT =1mA, Vout+2V≤VIN≤18 4
Output voltage temperature coefficient ΔVOUT/ΔTa -0.75 0.75 mV/℃ VDD=Vout+2V Iout=10mA; 0℃<Ta<70℃ 4

CAD (KiCad official)

  • Symbol: CL9975A25L3N
  • Footprint: Package_TO_SOT_SMD:SOT-23-3
  • 3D model: SOT-23-3L (KiCad packages3D, STEP)
  • 3D model files: cl9975a25l3n-etched.step / cl9975a25l3n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cl9975a25l3n.step / cl9975a25l3n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CHIPLINK(芯联) datasheet (8 pp, sha256 6c62ecc40b52235b, retrieved 2026-11-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF