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Contents

README

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CL9906A30F4N

CHIPLINK(芯联) · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-4(1x1)

CL9906A30F4N from CHIPLINK(芯联), in a DFN-4(1x1). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT power_out Regulated output pin; the datasheet limits VOUT pin voltage to GND-0.3 V to VIN+0.3 V and gives a VOUT pin current absolute maximum of 500 mA.
2 GND power_in Ground pin (接地端) for the regulator.
3 NC unconnected Empty pin (空脚) with no function on the DFN1*1-4 package.
4 VIN power_in Power input pin; the datasheet gives a VIN absolute maximum of -0.3 V to +7.0 V and a maximum input voltage of 6.5 V in the features list.
5 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer CHIPLINK(芯联)
Package DFN-4(1x1)
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN 6.5 V 7
Quiescent current IQ 1 uA 7
Output voltage VOUT 2.94 3 3.06 V VIN =4.0V, IOUT=30mA 7
Maximum output current IOUT (max) 200 mA VIN =4.0V 7
Load regulation ΔVOUT 20 mV VIN=4.0V, 1mA≤IOUT≤100mA 7
Load regulation ΔVOUT 40 mV VIN=4.0V, 1mA≤IOUT≤200mA 7
Dropout voltage Vdif1 65 mV IOUT =30mA 7
Dropout voltage Vdif2 220 mV IOUT =100mA 7
Line regulation ΔVOUT/(ΔVIN*VOUT) 0.05 %/V IOUT =30mA, 4.0≤VIN≤7V 7
Short-circuit current ISHORT 50 mA VIN =4.0V 7
Overcurrent protection current ILIMIT 300 mA VIN =4.0V 7
VIN pin voltage (absolute maximum) VIN -0.3 7 V 3
VOUT pin voltage (absolute maximum) VOUT -0.3 V Referenced to GND; printed as GND-0.3 ~ VIN+0.3 V, upper bound VIN+0.3 V is not a fixed number 3
VOUT pin current IOUT 500 mA Footnote (1): IOUT ≤ Pd/(VIN-VOUT) 3
Operating ambient temperature Topr -25 85 C 3
Storage temperature Tstg -40 125 C 3
Soldering temperature Tsolder 260 C 10s 3
Input capacitor range (test condition) CIN 1 10 uF Stated in the A30 electrical table header 7
Output capacitor range (test condition) COUT 1 10 uF Stated in the A30 electrical table header 7

CAD (KiCad official)

  • Symbol: CL9906A30F4N
  • Footprint: Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm
  • 3D model: DFN-4(1x1) (KiCad packages3D, STEP)
  • 3D model files: cl9906a30f4n-etched.step / cl9906a30f4n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cl9906a30f4n.step / cl9906a30f4n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CHIPLINK(芯联) datasheet (12 pp, sha256 defc25fc4da55cd3, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF