# CL9193A12L5M

**ChipLink Tech** · Linear Voltage Regulators (LDO) · SOT-23-5

CL9193A12L5M from ChipLink Tech, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input supply pin; absolute maximum 8 V, with recommended 1uF input capacitor and operating input up to 7.0 V. |
| 2 | GND | power_in | Ground pin. |
| 3 | CE | input | Chip enable input (EN in block diagram); shutdown when Vce = 0 V with shutdown current under 1 uA, tied to VIN in the typical application. |
| 4 | BP | passive | Bypass pin connected to the internal reference (VREF) with a 22nF capacitor to ground in the typical application for low noise. |
| 5 | VOUT | power_out | Regulated output delivering up to 300 mA, with 1uF output capacitor. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ChipLink Tech |
| Package | SOT-23-5 |
| Category | Power Supply Chip |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Vin pin voltage | VIN |  |  | 8 | V |  | 2 |
| Vout pin current | Iout |  |  | 500 | mA |  | 2 |
| Allowable power dissipation | Pd |  |  | 300 | mW | SOT23-5 package | 2 |
| Operating temperature | TOpr | -40 |  | 85 | ℃ |  | 2 |
| Storage temperature | Tstg | -55 |  | 125 | ℃ |  | 2 |
| Soldering temperature | Tsolder |  |  | 260 | ℃ | 10s | 2 |
| Output voltage (effective) | VOUT(E) | 0.98 |  | 1.02 | X VOUT(T) | IOUT=40mA, VIN=Vout+1V | 3 |
| Input voltage | VIN |  |  | 7 | V |  | 3 |
| Maximum output current | IOUTmax |  |  | 300 | mA | VIN=Vout+1V | 3 |
| Load regulation | ΔVOUT |  |  | 50 | mV | VIN=Vout+1V, 1mA≤IOUT≤100mA | 3 |
| Dropout voltage 1 | Vdif1 |  |  | 300 | mV | IOUT=100mA | 3 |
| Dropout voltage 2 | Vdif2 |  |  | 500 | mV | IOUT=200mA | 3 |
| Quiescent current | ISS |  | 80 |  | μA | VIN=Vout+1V | 3 |
| Shutdown current | ICEL |  |  | 1 | μA | Vce＝0V | 3 |
| Supply voltage regulation (line regulation) | ΔVOUT/ΔVIN•VOUT |  | 0.05 |  | %/V | IOUT=40mA, Vout+1V ≤VIN≤8V | 3 |
| Output noise | en |  | 50 |  | uVrms | IOUT=40mA, 300Hz~50kHz | 3 |
| Ripple rejection ratio | PSRR |  | 70 |  | dB | Vin=[Vout+1]V +1Vp-pAC, IOUT=40mA, f=1kHz | 3 |

## CAD (KiCad official)

- Symbol: `CL9193A12L5M`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `cl9193a12l5m-etched.step` / `cl9193a12l5m-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cl9193a12l5m.step` / `cl9193a12l5m.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ChipLink Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586200707086737408) (5 pp, sha256 `c17b85ef4997c9cf`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cl9193a12l5m-datasheet.pdf)