component
CL9036A30F4M
Public Made by Adomby adom
CHIPLINK(芯联) Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN-4(1x1). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CL9036A30F4M
CHIPLINK(芯联) · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-4(1x1)
CL9036A30F4M from CHIPLINK(芯联), in a DFN-4(1x1). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Regulated output pin; the output voltage is 1.2 V to 3.6 V (1.2 V to 3.6 V range per the features list), output current up to 400 mA, and the pin voltage is limited to Vss-0.3 V to Vout+0.3 V with a 450 mA absolute maximum output current. |
| 2 | GND | power_in | Ground pin; the CE-to-GND internal 1 MΩ resistor is referenced to this pin. |
| 3 | CE | input | Enable pin (EN), with a logic high threshold of 1.3 V minimum and a logic low threshold of 0.7 V maximum; the datasheet recommends driving it to 1.1 V for margin, and the pin voltage is limited to GND-0.3 V to VIN+0.3 V. |
| 4 | VIN | power_in | Supply input pin; the input voltage is rated 5.5 V maximum for operation with an absolute maximum of 6 V, and the datasheet tests specifications at VIN = Vout + 1 V. |
| 5 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CHIPLINK(芯联) |
| Package | DFN-4(1x1) |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage (regulated, as multiplier of VOUT(T)) | VOUT | 0.98 | 1.02 | x VOUT(T) | VIN=Vout+1V, IOUT=40mA; printed as *0.98 / *1.02 of VOUT(T); VOUT(T) not printed numerically for this variant | 4 | |
| Load regulation | ΔVOUT | 50 | mV | VIN=Vout+1V, 1mA≤IOUT≤100mA | 4 | ||
| Dropout voltage 1 | Vdif1 | 90 | mV | IOUT=100mA | 4 | ||
| Dropout voltage 2 | Vdif2 | 200 | mV | IOUT=200mA | 4 | ||
| Line regulation (supply voltage regulation) | ΔVOUT/(ΔVIN*VOUT) | 0.05 | %/V | IOUT=40mA, Vout+1V≤VIN≤8V | 4 | ||
| CE high-level input voltage | VCEH | 1.3 | V | 4 | |||
| CE low-level input voltage | VCEL | 0.7 | V | 4 | |||
| Output noise voltage | en | 50 | uVrms | IOUT=40mA, 300Hz~50kHz | 4 | ||
| Ripple rejection ratio | PSRR | 75 | dB | VIN=[Vout+1]V +1Vp-pAC, IOUT=40mA, f=1kHz | 4 | ||
| Maximum output current | IOUT(max) | 400 | mA | VIN=Vout+1V | 4 | ||
| VIN pin voltage (absolute maximum) | VIN | 6 | V | 3 | |||
| VOUT pin output current (absolute maximum) | IOUT | 450 | mA | 3 | |||
| Operating ambient temperature | Topr | -25 | 85 | C | 3 | ||
| Storage temperature | Tstg | -40 | 125 | C | 3 | ||
| Soldering temperature and time | Tsolder | 260 | C | 10s | 3 | ||
| Package power dissipation | Pd | 500 | mW | UTDFN-1*1-4L package | 3 | ||
| Input voltage range | VIN | 5.5 | V | 4 | |||
| Quiescent current | IQ | 70 | uA | VIN=Vout+1V | 4 | ||
| CE pin internal resistance to GND | 1 | MΩ | CE pin to GND pin, built-in (per note) | 4 | |||
| ESD human body model | 2000 | V | Human body model, printed as >2000V | 2 | |||
| ESD machine model | 200 | V | Machine model, printed as >200V | 2 | |||
| Latch-up level | 200 | mA | printed as >200mA | 2 |
CAD (KiCad official)
- Symbol:
CL9036A30F4M - Footprint:
Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm - 3D model: DFN-4(1x1) (KiCad packages3D, STEP)
- 3D model files:
cl9036a30f4m-etched.step/cl9036a30f4m-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cl9036a30f4m.step/cl9036a30f4m.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CHIPLINK(芯联) datasheet (6 pp, sha256
d29f555afd34e34b, retrieved 2026-10-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CL9036A30F4M
**CHIPLINK(芯联)** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-4(1x1)
CL9036A30F4M from CHIPLINK(芯联), in a DFN-4(1x1). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Regulated output pin; the output voltage is 1.2 V to 3.6 V (1.2 V to 3.6 V range per the features list), output current up to 400 mA, and the pin voltage is limited to Vss-0.3 V to Vout+0.3 V with a 450 mA absolute maximum output current. |
| 2 | GND | power_in | Ground pin; the CE-to-GND internal 1 MΩ resistor is referenced to this pin. |
| 3 | CE | input | Enable pin (EN), with a logic high threshold of 1.3 V minimum and a logic low threshold of 0.7 V maximum; the datasheet recommends driving it to 1.1 V for margin, and the pin voltage is limited to GND-0.3 V to VIN+0.3 V. |
| 4 | VIN | power_in | Supply input pin; the input voltage is rated 5.5 V maximum for operation with an absolute maximum of 6 V, and the datasheet tests specifications at VIN = Vout + 1 V. |
| 5 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CHIPLINK(芯联) |
| Package | DFN-4(1x1) |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage (regulated, as multiplier of VOUT(T)) | VOUT | 0.98 | | 1.02 | x VOUT(T) | VIN=Vout+1V, IOUT=40mA; printed as *0.98 / *1.02 of VOUT(T); VOUT(T) not printed numerically for this variant | 4 |
| Load regulation | ΔVOUT | | | 50 | mV | VIN=Vout+1V, 1mA≤IOUT≤100mA | 4 |
| Dropout voltage 1 | Vdif1 | | | 90 | mV | IOUT=100mA | 4 |
| Dropout voltage 2 | Vdif2 | | | 200 | mV | IOUT=200mA | 4 |
| Line regulation (supply voltage regulation) | ΔVOUT/(ΔVIN*VOUT) | | | 0.05 | %/V | IOUT=40mA, Vout+1V≤VIN≤8V | 4 |
| CE high-level input voltage | VCEH | 1.3 | | | V | | 4 |
| CE low-level input voltage | VCEL | | | 0.7 | V | | 4 |
| Output noise voltage | en | | | 50 | uVrms | IOUT=40mA, 300Hz~50kHz | 4 |
| Ripple rejection ratio | PSRR | 75 | | | dB | VIN=[Vout+1]V +1Vp-pAC, IOUT=40mA, f=1kHz | 4 |
| Maximum output current | IOUT(max) | | | 400 | mA | VIN=Vout+1V | 4 |
| VIN pin voltage (absolute maximum) | VIN | | | 6 | V | | 3 |
| VOUT pin output current (absolute maximum) | IOUT | | | 450 | mA | | 3 |
| Operating ambient temperature | Topr | -25 | | 85 | C | | 3 |
| Storage temperature | Tstg | -40 | | 125 | C | | 3 |
| Soldering temperature and time | Tsolder | | | 260 | C | 10s | 3 |
| Package power dissipation | Pd | | | 500 | mW | UTDFN-1*1-4L package | 3 |
| Input voltage range | VIN | | | 5.5 | V | | 4 |
| Quiescent current | IQ | | 70 | | uA | VIN=Vout+1V | 4 |
| CE pin internal resistance to GND | | | 1 | | MΩ | CE pin to GND pin, built-in (per note) | 4 |
| ESD human body model | | 2000 | | | V | Human body model, printed as >2000V | 2 |
| ESD machine model | | 200 | | | V | Machine model, printed as >200V | 2 |
| Latch-up level | | 200 | | | mA | printed as >200mA | 2 |
## CAD (KiCad official)
- Symbol: `CL9036A30F4M`
- Footprint: `Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm`
- 3D model: DFN-4(1x1) (KiCad packages3D, STEP)
- 3D model files: `cl9036a30f4m-etched.step` / `cl9036a30f4m-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cl9036a30f4m.step` / `cl9036a30f4m.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [CHIPLINK(芯联) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904493934792704) (6 pp, sha256 `d29f555afd34e34b`, retrieved 2026-10-27, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cl9036a30f4m-datasheet.pdf)