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CL4056H
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ChipLink Tech Battery Management ICs, ESOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CL4056H
ChipLink Tech · Battery Management ICs · ESOP-8
CL4056H from ChipLink Tech, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TEMP | input | Battery thermistor input; charging paused if voltage exceeds 80% VCC or drops below 45% VCC. |
| 2 | PROG | input | Charging current programming pin; resistor to GND sets charging current (typical voltage 1.0V in constant-current mode). |
| 3 | GND | power_in | Ground reference. |
| 4 | VCC | power_in | Power supply input; operating range 4.0 to 6.5V, absolute maximum 30V. |
| 5 | BAT | bidirectional | Battery terminal; float voltage 4.24V for lithium-ion cells, 1A maximum charging current, absolute range -0.3V to 18V. |
| 6 | STDBY | tri_state | Open-drain charging-complete status output; pulled low (0.35-0.6V @ 5mA) when charging finished, otherwise high impedance. |
| 7 | CHRG | tri_state | Open-drain charging-in-progress status output; pulled low (0.35-0.6V @ 5mA) during active charging, otherwise high impedance. |
| 8 | CE | input | Chip enable control input; charging operation enabled when logic high, disabled when logic low. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ChipLink Tech |
| Package | ESOP-8 |
| Category | Power Supply Chip |
| Pins | 9 |
CAD (KiCad official)
- Symbol:
CL4056H - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files:
cl4056h-etched.step/cl4056h-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cl4056h.step/cl4056h.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ChipLink Tech datasheet (11 pp, sha256
2deca520cf262fb7, retrieved 2026-09-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CL4056H
**ChipLink Tech** · Battery Management ICs · ESOP-8
CL4056H from ChipLink Tech, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TEMP | input | Battery thermistor input; charging paused if voltage exceeds 80% VCC or drops below 45% VCC. |
| 2 | PROG | input | Charging current programming pin; resistor to GND sets charging current (typical voltage 1.0V in constant-current mode). |
| 3 | GND | power_in | Ground reference. |
| 4 | VCC | power_in | Power supply input; operating range 4.0 to 6.5V, absolute maximum 30V. |
| 5 | BAT | bidirectional | Battery terminal; float voltage 4.24V for lithium-ion cells, 1A maximum charging current, absolute range -0.3V to 18V. |
| 6 | STDBY | tri_state | Open-drain charging-complete status output; pulled low (0.35-0.6V @ 5mA) when charging finished, otherwise high impedance. |
| 7 | CHRG | tri_state | Open-drain charging-in-progress status output; pulled low (0.35-0.6V @ 5mA) during active charging, otherwise high impedance. |
| 8 | CE | input | Chip enable control input; charging operation enabled when logic high, disabled when logic low. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ChipLink Tech |
| Package | ESOP-8 |
| Category | Power Supply Chip |
| Pins | 9 |
## CAD (KiCad official)
- Symbol: `CL4056H`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`
- 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files: `cl4056h-etched.step` / `cl4056h-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cl4056h.step` / `cl4056h.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [ChipLink Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590234900243505152) (11 pp, sha256 `2deca520cf262fb7`, retrieved 2026-09-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cl4056h-datasheet.pdf)