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CKS32F407VGT6

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CKS Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscks32f407vgt6factory-2.0.0extractor-text
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Contents

README

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CKS32F407VGT6

CKS · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

CKS32F407VGT6 from CKS, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional I/O, 5 V tolerant (FT); alternate functions include TRACECLK, FSMC_A23, ETH_MII_TXD3 and EVENTOUT.
2 PE3 bidirectional I/O, 5 V tolerant (FT); alternate functions include TRACE0, FSMC_A19 and EVENTOUT.
3 PE4 bidirectional I/O, 5 V tolerant (FT); alternate functions include TRACE1, FSMC_A20, DCMI_D4 and EVENTOUT.
4 PE5 bidirectional I/O, 5 V tolerant (FT); alternate functions include TRACE2, FSMC_A21, TIM9_CH1, DCMI_D6 and EVENTOUT.
5 PE6 bidirectional I/O, 5 V tolerant (FT); alternate functions include TRACE3, FSMC_A22, TIM9_CH2, DCMI_D7 and EVENTOUT.
6 VBAT power_in Backup supply of 1.65-3.6 V for the RTC, backup registers and backup SRAM when VDD is absent; it must not be left floating and must be supplied from VDD if no external backup source is used.
7 PC13 bidirectional I/O, FT, fed through the power switch: limited to 3 mA, at most 2 MHz with 30 pF load in output mode, and must not be used as a current source (e.g. LED drive); additional functions RTC_OUT, RTC_TAMP1 and RTC_TS.
8 PC14 bidirectional I/O, FT, fed through the power switch with the same limits as PC13 (3 mA, 2 MHz at 30 pF, no current-source use); additional function OSC32_IN for the 32.768 kHz crystal.
9 PC15 bidirectional I/O, FT, fed through the power switch with the same limits as PC13 (3 mA, 2 MHz at 30 pF, no current-source use); additional function OSC32_OUT for the 32.768 kHz crystal.
10 VSS power_in Ground; all VSS pins must be connected to the external ground of the supply system.
11 VDD power_in Supply of 1.8-3.6 V for the I/O pins and the internal voltage regulator.
12 PH0 bidirectional I/O, FT; additional function OSC_IN, the input of the high-speed external oscillator (4-26 MHz crystal/resonator).
13 PH1 bidirectional I/O, FT; additional function OSC_OUT, the output of the high-speed external oscillator (4-26 MHz crystal/resonator).
14 NRST bidirectional Bidirectional reset pin with an internal weak pull-up resistor (RPU 30-50 kΩ, 40 kΩ typical).
15 PC0 bidirectional I/O, FT; alternate function OTG_HS_ULPI_STP and EVENTOUT; additional function ADC123_IN10 analog input.
16 PC1 bidirectional I/O, FT; alternate function ETH_MDC and EVENTOUT; additional function ADC123_IN11 analog input.
17 PC2 bidirectional I/O, FT; alternate functions SPI2_MISO, OTG_HS_ULPI_DIR, ETH_MII_TXD2, I2S2ext_SD and EVENTOUT; additional function ADC123_IN12 analog input.
18 PC3 bidirectional I/O, FT; alternate functions SPI2_MOSI, I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK and EVENTOUT; additional function ADC123_IN13 analog input.
19 VDD power_in Supply of 1.8-3.6 V for the I/O pins and the internal voltage regulator.
20 VSSA power_in Analog ground for the ADC, DAC, reset block, RC oscillators and PLL; must be connected to VSS.
21 VREF+ power_in Positive reference voltage for the ADC and DAC; the datasheet requires VDDA − VREF+ < 1.2 V when this pin is present.
22 VDDA power_in Analog supply of 1.8-3.6 V for the ADC, DAC, reset block, RC oscillators and PLL; must be connected to VDD.
23 PA0/WKUP bidirectional I/O, FT; WKUP wake-up function and ADC123_IN0 analog input; alternate functions include USART2_CTS, UART4_TX, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR and EVENTOUT.
24 PA1 bidirectional I/O, FT; alternate functions include USART2_RTS, UART4_RX, ETH_RMII_REF_CLK, TIM5_CH2 and TIM2_CH2; additional function ADC123_IN1.
25 PA2 bidirectional I/O, FT; alternate functions include USART2_TX, TIM5_CH3, TIM9_CH1, TIM2_CH3 and ETH_MDIO; additional function ADC123_IN2.
26 PA3 bidirectional I/O, FT; alternate functions include USART2_RX, TIM5_CH4, TIM9_CH2, TIM2_CH4 and OTG_HS_ULPI_D0; additional function ADC123_IN3.
27 VSS power_in Ground; all VSS pins must be connected to the external ground of the supply system.
28 VDD power_in Supply of 1.8-3.6 V for the I/O pins and the internal voltage regulator.
29 PA4 bidirectional I/O, TTa (3.3 V tolerant, connected directly to the ADC); alternate functions include SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC and I2S3_WS; additional functions ADC12_IN4 and DAC_OUT1.
30 PA5 bidirectional I/O, TTa (3.3 V tolerant, connected directly to the ADC); alternate functions include SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR and TIM8_CH1N; additional functions ADC12_IN5 and DAC_OUT2.
31 PA6 bidirectional I/O, FT; alternate functions include SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1 and TIM1_BKIN; additional function ADC12_IN6.
32 PA7 bidirectional I/O, FT; alternate functions include SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, ETH_MII_RX_DV and ETH_RMII_CRS_DV; additional function ADC12_IN7.
33 PC4 bidirectional I/O, FT; alternate functions ETH_RMII_RX_D0 and ETH_MII_RX_D0 with EVENTOUT; additional function ADC12_IN14.
34 PC5 bidirectional I/O, FT; alternate functions ETH_RMII_RX_D1 and ETH_MII_RX_D1 with EVENTOUT; additional function ADC12_IN15.
35 PB0 bidirectional I/O, FT; alternate functions include TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2 and TIM1_CH2N; additional function ADC12_IN8.
36 PB1 bidirectional I/O, FT; alternate functions include TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3 and TIM1_CH3N; additional function ADC12_IN9.
37 PB2/BOOT1 bidirectional I/O, FT; shared with BOOT1, part of the boot-mode selection; alternate function EVENTOUT.
38 PE7 bidirectional I/O, FT; alternate functions FSMC_D4, TIM1_ETR and EVENTOUT.
39 PE8 bidirectional I/O, FT; alternate functions FSMC_D5, TIM1_CH1N and EVENTOUT.
40 PE9 bidirectional I/O, FT; alternate functions FSMC_D6, TIM1_CH1 and EVENTOUT.
41 PE10 bidirectional I/O, FT; alternate functions FSMC_D7, TIM1_CH2N and EVENTOUT.
42 PE11 bidirectional I/O, FT; alternate functions FSMC_D8, TIM1_CH2 and EVENTOUT.
43 PE12 bidirectional I/O, FT; alternate functions FSMC_D9, TIM1_CH3N and EVENTOUT.
44 PE13 bidirectional I/O, FT; alternate functions FSMC_D10, TIM1_CH3 and EVENTOUT.
45 PE14 bidirectional I/O, FT; alternate functions FSMC_D11, TIM1_CH4 and EVENTOUT.
46 PE15 bidirectional I/O, FT; alternate functions FSMC_D12, TIM1_BKIN and EVENTOUT.
47 PB10 bidirectional I/O, FT; alternate functions include SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER and TIM2_CH3.
48 PB11 bidirectional I/O, FT; alternate functions include I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_RMII_TX_EN, ETH_MII_TX_EN and TIM2_CH4.
49 VCAP_1 power_out Main regulator stabilization pin; requires an external 2.2 µF capacitor with ESR < 2 Ω, or two 100 nF decoupling capacitors when the regulator is off.
50 VDD power_in Supply of 1.8-3.6 V for the I/O pins and the internal voltage regulator.
51 PB12 bidirectional I/O, FT; alternate functions include SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, OTG_HS_ULPI_D5, ETH_RMII_TXD0 and OTG_HS_ID.
52 PB13 bidirectional I/O, FT; alternate functions include SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, OTG_HS_ULPI_D6 and ETH_RMII_TXD1; additional function OTG_HS_VBUS.
53 PB14 bidirectional I/O, FT; alternate functions include SPI2_MISO, TIM1_CH2N, TIM12_CH1, OTG_HS_DM, USART3_RTS, TIM8_CH2N and I2S2ext_SD.
54 PB15 bidirectional I/O, FT; alternate functions include SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM8_CH3N, TIM12_CH2 and OTG_HS_DP; additional function RTC_REFIN.
55 PD8 bidirectional I/O, FT; alternate functions FSMC_D13 and USART3_TX with EVENTOUT.
56 PD9 bidirectional I/O, FT; alternate functions FSMC_D14 and USART3_RX with EVENTOUT.
57 PD10 bidirectional I/O, FT; alternate functions FSMC_D15 and USART3_CK with EVENTOUT.
58 PD11 bidirectional I/O, FT; alternate functions FSMC_CLE, FSMC_A16 and USART3_CTS with EVENTOUT.
59 PD12 bidirectional I/O, FT; alternate functions FSMC_ALE, FSMC_A17, TIM4_CH1 and USART3_RTS with EVENTOUT.
60 PD13 bidirectional I/O, FT; alternate functions FSMC_A18 and TIM4_CH2 with EVENTOUT.
61 PD14 bidirectional I/O, FT; alternate functions FSMC_D0 and TIM4_CH3 with EVENTOUT.
62 PD15 bidirectional I/O, FT; alternate functions FSMC_D1 and TIM4_CH4 with EVENTOUT.
63 PC6 bidirectional I/O, FT; alternate functions include I2S2_MCK, TIM8_CH1, SDIO_D6, USART6_TX, DCMI_D0 and TIM3_CH1.
64 PC7 bidirectional I/O, FT; alternate functions include I2S3_MCK, TIM8_CH2, SDIO_D7, USART6_RX, DCMI_D1 and TIM3_CH2.
65 PC8 bidirectional I/O, FT; alternate functions include TIM8_CH3, SDIO_D0, TIM3_CH3, USART6_CK and DCMI_D2.
66 PC9 bidirectional I/O, FT; alternate functions include I2S_CKIN, MCO2, TIM8_CH4, SDIO_D1, I2C3_SDA, DCMI_D3 and TIM3_CH4.
67 PA8 bidirectional I/O, FT; alternate functions include MCO1, USART1_CK, TIM1_CH1, I2C3_SCL and OTG_FS_SOF.
68 PA9 bidirectional I/O, FT; alternate functions include USART1_TX, TIM1_CH2, I2C3_SMBA and DCMI_D0; additional function OTG_FS_VBUS.
69 PA10 bidirectional I/O, FT; alternate functions include USART1_RX, TIM1_CH3, OTG_FS_ID and DCMI_D1.
70 PA11 bidirectional I/O, FT; alternate functions include USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM.
71 PA12 bidirectional I/O, FT; alternate functions include USART1_RTS, CAN1_TX, TIM1_ETR and OTG_FS_DP.
72 PA13 bidirectional I/O, FT; alternate function JTMS-SWDIO, the serial-wire debug data pin shared with JTAG TMS.
73 VCAP_2 power_out Main regulator stabilization pin; requires an external 2.2 µF capacitor with ESR < 2 Ω, or two 100 nF decoupling capacitors when the regulator is off.
74 VSS power_in Ground; all VSS pins must be connected to the external ground of the supply system.
75 VDD power_in Supply of 1.8-3.6 V for the I/O pins and the internal voltage regulator.
76 PA14 bidirectional I/O, FT; alternate function JTCK-SWCLK, the serial-wire debug clock pin shared with JTAG TCK.
77 PA15 bidirectional I/O, FT; alternate functions include JTDI, SPI3_NSS, I2S3_WS, TIM2_CH1_ETR and SPI1_NSS.
78 PC10 bidirectional I/O, FT; alternate functions include SPI3_SCK, I2S3_CK, UART4_TX, SDIO_D2, DCMI_D8 and USART3_TX.
79 PC11 bidirectional I/O, FT; alternate functions include UART4_RX, SPI3_MISO, SDIO_D3, DCMI_D4, USART3_RX and I2S3ext_SD.
80 PC12 bidirectional I/O, FT; alternate functions include UART5_TX, SDIO_CK, DCMI_D9, SPI3_MOSI, I2S3_SD and USART3_CK.
81 PD0 bidirectional I/O, FT; alternate functions FSMC_D2 and CAN1_RX with EVENTOUT.
82 PD1 bidirectional I/O, FT; alternate functions FSMC_D3 and CAN1_TX with EVENTOUT.
83 PD2 bidirectional I/O, FT; alternate functions include TIM3_ETR, UART5_RX, SDIO_CMD and DCMI_D11 with EVENTOUT.
84 PD3 bidirectional I/O, FT; alternate functions FSMC_CLK and USART2_CTS with EVENTOUT.
85 PD4 bidirectional I/O, FT; alternate functions FSMC_NOE and USART2_RTS with EVENTOUT.
86 PD5 bidirectional I/O, FT; alternate functions FSMC_NWE and USART2_TX with EVENTOUT.
87 PD6 bidirectional I/O, FT; alternate functions FSMC_NWAIT and USART2_RX with EVENTOUT.
88 PD7 bidirectional I/O, FT; alternate functions USART2_CK, FSMC_NE1 and FSMC_NCE2 with EVENTOUT.
89 PB3 bidirectional I/O, FT; alternate functions include JTDO/TRACESWO, SPI3_SCK, I2S3_CK, TIM2_CH2 and SPI1_SCK.
90 PB4 bidirectional I/O, FT; alternate functions include NJTRST, SPI3_MISO, TIM3_CH1, SPI1_MISO and I2S3ext_SD.
91 PB5 bidirectional I/O, FT; alternate functions include I2C1_SMBA, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, TIM3_CH2, SPI1_MOSI, SPI3_MOSI, DCMI_D10 and I2S3_SD.
92 PB6 bidirectional I/O, FT; alternate functions include I2C1_SCL, TIM4_CH1, CAN2_TX, DCMI_D5 and USART1_TX.
93 PB7 bidirectional I/O, FT; alternate functions include I2C1_SDA, FSMC_NL, DCMI_VSYNC, USART1_RX and TIM4_CH2.
94 BOOT0 input Boot-mode selection input (also listed as VPP) whose input voltage is limited to 5.5 V.
95 PB8 bidirectional I/O, FT; alternate functions include TIM4_CH3, SDIO_D4, TIM10_CH1, DCMI_D6, ETH_MII_TXD3, I2C1_SCL and CAN1_RX.
96 PB9 bidirectional I/O, FT; alternate functions include SPI2_NSS, I2S2_WS, TIM4_CH4, TIM11_CH1, SDIO_D5, DCMI_D7, I2C1_SDA and CAN1_TX.
97 PE0 bidirectional I/O, FT; alternate functions TIM4_ETR, FSMC_NBL0 and DCMI_D2 with EVENTOUT.
98 PE1 bidirectional I/O, FT; alternate functions FSMC_NBL1 and DCMI_D3 with EVENTOUT.
99 VSS power_in Ground; all VSS pins must be connected to the external ground of the supply system.
100 VDD power_in Supply of 1.8-3.6 V for the I/O pins and the internal voltage regulator.

Key specifications

Parameter Value
Manufacturer CKS
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
ESD human body model (HBM) voltage VESD(HBM) 2000 V T = +25 °C, JESD22-A114 72
ESD charged device model (CDM) voltage VESD(CDM) 500 V T = +25 °C, ANSI/ESD 72
I/O injection current, other pins (functional susceptibility) IINJ -5 5 mA 73
I/O injection current, all FT pins (negative injection) IINJ -5 mA 73
I/O input leakage current Ilkg -1 1 μA VSS ≤ VIN ≤ VDD 74
I/O FT input leakage current 3 μA VIN = 5V 74
Weak pull-up equivalent resistance, all pins except PA10 and PB12 RPU 30 40 50 kΩ VIN = VSS 74
Weak pull-up equivalent resistance, PA10 and PB12 RPU 7 10 14 kΩ 74
Weak pull-down equivalent resistance, all pins except PA10 and PB12 RPD 30 40 50 kΩ VIN = VDD 74
Weak pull-down equivalent resistance, PA10 and PB12 RPD 7 10 14 kΩ 74
I/O pin capacitance CIO 5 pF 74
GPIO sink or source output current -8 8 mA 74
GPIO sink or source output current (relaxed VOL/VOH) -20 20 mA relaxed VOL/VOH 74
PC13, PC14, PC15 sink or source output current -3 3 mA 74
USB OTG FS transceiver startup time tSTARTUP 1 μs 82
USB OTG FS operating voltage VDD 3 3.6 V 83
USB differential input sensitivity VDI 0.2 V I(USB_FS_DP/DM, USB_HS_DP/DM) 83
USB differential common mode range VCM 0.8 2.5 V includes VDI range 83
USB single-ended receiver threshold VSE 1.3 2 V 83
USB static output low VOL 0.3 V RL = 1.5kΩ connected to 3.6V 83
USB static output high VOH 2.8 3.6 V RL = 15kΩ connected to ground 83
USB pull-down resistance, PA11, PA12, PB14, PB15 RPD 17 21 24 kΩ VIN=VDD 83
USB pull-down resistance, PA9, PB13 RPD 0.65 1.1 2 kΩ 83
USB pull-up resistance, PA12, PB15 RPU 1.5 1.8 2.1 kΩ VIN=VSS 83
USB pull-up resistance, PA9, PB13 RPU 0.25 0.37 0.55 kΩ VIN=VSS 83
USB full-speed rise time tr 4 20 ns CL ≤ 50pF 84
USB full-speed fall time tf 4 20 ns CL ≤ 50pF 84
USB rise/fall time matching trfm 90 110 % 84
USB output signal crossover voltage VCRS 1.3 2 V 84
USB OTG HS operating voltage VDD 2.7 3.6 V 84
USB HS frequency at first transition (8-bit ±10%) FSTART_8BIT 54 60 66 MHz 8位±10% 84
USB HS frequency at steady state FSTEADY 59.97 60 60.03 MHz ±500ppm 84
USB HS duty cycle at first transition (8-bit ±10%) DSTEADY_8BIT 40 50 60 % 8位±10% 84
USB HS duty cycle at steady state DSTEADY 49.975 50 50.025 % ±500ppm 84
Time to reach steady-state frequency and duty cycle after first transition TSTEADY 1.4 ms 84
Clock start-up time after SuspendM de-assertion, peripheral TSTART_DEV 5.6 ms 84
ULPI control input (ULPI_DIR) setup time tSC 2 ns 84
ULPI control input (ULPI_NXT) setup time 1.5 ns 84
ULPI control input (ULPI_DIR, ULPI_NXT) hold time tHC 0 ns 84
ULPI data setup time tSD 2 ns 84
ULPI data hold time tHD 0 ns 84
ULPI control output (ULPI_STP) setup and hold time tDC 9.2 ns 85
ULPI data valid time after clock rising edge tDD 10.7 ns 85
Ethernet operating voltage VDD 2.7 3.6 V 85
SMI MDC clock period tMDC 411 420 425 ns MDC clock frequency 2.38MHz 85
SMI write data valid time Td(MDIO) 6 10 13 ns 85
SMI read data setup time tsu(MDIO) 12 ns 85
SMI read data hold time th(MDIO) 0 ns 85
RMII receive data setup time tsu(RXD) 2 ns 86
RMII receive data hold time tih(RXD) 1 ns 86
RMII carrier sense setup time tsu(CRS) 0.5 ns 86
RMII carrier sense hold time tih(CRS) 2 ns 86
RMII transmit enable valid delay td(TXEN) 8 9.5 11 ns 86
RMII transmit data valid delay td(TXD) 8.5 10 11.5 ns 86
MII receive data setup time tsu(RXD) 9 ns 86
MII receive data hold time tih(RXD) 10 ns 86
MII data valid setup time tsu(DV) 9 ns 86
MII data valid hold time tih(DV) 8 ns 86
Supply voltage (features summary, supply and I/O pins) 1.8 3.6 V supply and I/O pins 1

CAD (KiCad official)

  • Symbol: CKS32F407VGT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: cks32f407vgt6-etched.step / cks32f407vgt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cks32f407vgt6.step / cks32f407vgt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CKS datasheet (123 pp, sha256 09eb7889abf142f1, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF