component
CKS32F405RGT6
Public Made by Adomby adom
CKS Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCKS32F405RGT6
CKS · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
CKS32F405RGT6 from CKS, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply (1.65-3.6 V) for the RTC, backup registers and backup SRAM; it must not be left floating and should be powered from VDD when no external battery is used. |
| 2 | PC13 | bidirectional | 5 V-tolerant GPIO (FT) on the power-switched supply; in output mode it is limited to 2 MHz at 30 pF maximum load and must not be used as a current source such as an LED driver. |
| 3 | PC14 | bidirectional | 5 V-tolerant GPIO (FT) on the power-switched supply with the same output limits (2 MHz at 30 pF, no current sourcing); it doubles as OSC32_IN for the 32.768 kHz oscillator. |
| 4 | PC15 | bidirectional | 5 V-tolerant GPIO (FT) on the power-switched supply with the same output limits (2 MHz at 30 pF, no current sourcing); it doubles as OSC32_OUT for the 32.768 kHz oscillator. |
| 5 | PH0 | bidirectional | 5 V-tolerant GPIO (FT, except in oscillator mode) that serves as OSC_IN for the 4-26 MHz external crystal/resonator. |
| 6 | PH1 | bidirectional | 5 V-tolerant GPIO (FT, except in oscillator mode) that serves as OSC_OUT for the 4-26 MHz external crystal/resonator. |
| 7 | NRST | bidirectional | Bidirectional active-low reset pin with an internal weak pull-up resistor. |
| 8 | PC0 | bidirectional | 5 V-tolerant GPIO (FT) with alternate function OTG_HS_ULPI_STP and EVENTOUT, and analog input ADC123_IN10. |
| 9 | PC1 | bidirectional | 5 V-tolerant GPIO (FT) with alternate function ETH_MDC and EVENTOUT, and analog input ADC123_IN11. |
| 10 | PC2 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions SPI2_MISO, I2S2ext_SD, OTG_HS_ULPI_DIR and ETH_MII_TXD2, and analog input ADC123_IN12. |
| 11 | PC3 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions SPI2_MOSI, I2S2_SD, OTG_HS_ULPI_NXT and ETH_MII_TX_CLK, and analog input ADC123_IN13. |
| 12 | VSSA | power_in | Analog ground for the ADC, DAC, reset block, RC oscillators and PLL; it must be connected to VSS. |
| 13 | VDDA | power_in | Analog supply (1.8-3.6 V) for the ADC, DAC, reset block, RC oscillators and PLL; it must be connected to VDD. |
| 14 | PA0/WKUP | bidirectional | 5 V-tolerant GPIO (FT) with WKUP wake-up function, alternate functions USART2_CTS, UART4_TX, TIM2_CH1_ETR, TIM5_CH1 and TIM8_ETR, and analog input ADC123_IN0. |
| 15 | PA1 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions USART2_RTS, UART4_RX, TIM5_CH2 and TIM2_CH2, and analog input ADC123_IN1. |
| 16 | PA2 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions USART2_TX, TIM5_CH3, TIM9_CH1 and ETH_MDIO, and analog input ADC123_IN2. |
| 17 | PA3 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions USART2_RX, TIM5_CH4, TIM9_CH2 and TIM2_CH4, and analog input ADC123_IN3. |
| 18 | VSS | power_in | Ground reference for the device; all voltages are referenced to VSS. |
| 19 | VDD | power_in | Supply (1.8-3.6 V) for the I/O pins and the internal voltage regulator. |
| 20 | PA4 | bidirectional | 3.3 V-tolerant TTa I/O connected directly to the ADC, with alternate functions SPI1_NSS, SPI3_NSS, I2S3_WS, USART2_CK, DCMI_HSYNC and OTG_HS_SOF, and analog functions ADC12_IN4 and DAC_OUT1. |
| 21 | PA5 | bidirectional | 3.3 V-tolerant TTa I/O connected directly to the ADC, with alternate functions SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR and TIM8_CH1N, and analog functions ADC12_IN5 and DAC_OUT2. |
| 22 | PA6 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1 and TIM1_BKIN, and analog input ADC12_IN6. |
| 23 | PA7 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, ETH_MII_RX_DV and ETH_RMII_CRS_DV, and analog input ADC12_IN7. |
| 24 | PC4 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions ETH_RMII_RX_D0 and ETH_MII_RX_D0, and analog input ADC12_IN14. |
| 25 | PC5 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions ETH_RMII_RX_D1 and ETH_MII_RX_D1, and analog input ADC12_IN15. |
| 26 | PB0 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2 and TIM1_CH2N, and analog input ADC12_IN8. |
| 27 | PB1 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3 and TIM1_CH3N, and analog input ADC12_IN9. |
| 28 | PB2/BOOT1 | bidirectional | 5 V-tolerant GPIO (FT) with EVENTOUT function; the pin is also labelled BOOT1. |
| 29 | PB10 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER and TIM2_CH3. |
| 30 | PB11 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN, ETH_RMII_TX_EN and TIM2_CH4. |
| 31 | VCAP_1 | power_out | Main regulator stabilisation pin; connect an external capacitor of 2.2 µF with ESR below 2 Ω. |
| 32 | VDD | power_in | Supply (1.8-3.6 V) for the I/O pins and the internal voltage regulator. |
| 33 | PB12 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0 and OTG_HS_ID. |
| 34 | PB13 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, OTG_HS_ULPI_D6 and ETH_RMII_TXD1, with OTG_HS_VBUS listed as an additional function. |
| 35 | PB14 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions SPI2_MISO, I2S2ext_SD, USART3_RTS, TIM1_CH2N, TIM8_CH2N, TIM12_CH1 and OTG_HS_DM. |
| 36 | PB15 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM8_CH3N, TIM12_CH2 and OTG_HS_DP, with RTC_REFIN listed as an additional function. |
| 37 | PC6 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions I2S2_MCK, TIM8_CH1, SDIO_D6, USART6_TX, DCMI_D0 and TIM3_CH1. |
| 38 | PC7 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions I2S3_MCK, TIM8_CH2, SDIO_D7, USART6_RX, DCMI_D1 and TIM3_CH2. |
| 39 | PC8 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions TIM8_CH3, SDIO_D0, TIM3_CH3, USART6_CK and DCMI_D2. |
| 40 | PC9 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions I2S_CKIN, MCO2, TIM8_CH4, SDIO_D1, I2C3_SDA, DCMI_D3 and TIM3_CH4. |
| 41 | PA8 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions MCO1, USART1_CK, TIM1_CH1, I2C3_SCL and OTG_FS_SOF. |
| 42 | PA9 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions USART1_TX, TIM1_CH2, I2C3_SMBA and DCMI_D0, with OTG_FS_VBUS listed as an additional function. |
| 43 | PA10 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions USART1_RX, TIM1_CH3, OTG_FS_ID and DCMI_D1. |
| 44 | PA11 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM. |
| 45 | PA12 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions USART1_RTS, CAN1_TX, TIM1_ETR and OTG_FS_DP. |
| 46 | PA13 | bidirectional | 5 V-tolerant GPIO (FT) that carries the JTMS-SWDIO serial-wire debug data function. |
| 47 | VCAP_2 | power_out | Main regulator stabilisation pin; connect an external capacitor of 2.2 µF with ESR below 2 Ω. |
| 48 | VDD | power_in | Supply (1.8-3.6 V) for the I/O pins and the internal voltage regulator. |
| 49 | PA14 | bidirectional | 5 V-tolerant GPIO (FT) that carries the JTCK-SWCLK serial-wire debug clock function. |
| 50 | PA15 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions JTDI, SPI3_NSS, I2S3_WS, TIM2_CH1_ETR and SPI1_NSS. |
| 51 | PC10 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions SPI3_SCK, I2S3_CK, UART4_TX, SDIO_D2, DCMI_D8 and USART3_TX. |
| 52 | PC11 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions UART4_RX, SPI3_MISO, SDIO_D3, DCMI_D4, USART3_RX and I2S3ext_SD. |
| 53 | PC12 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions UART5_TX, SDIO_CK, DCMI_D9, SPI3_MOSI, I2S3_SD and USART3_CK. |
| 54 | PD2 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions TIM3_ETR, UART5_RX, SDIO_CMD and DCMI_D11. |
| 55 | PB3 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions JTDO/TRACESWO, SPI3_SCK, I2S3_CK, TIM2_CH2 and SPI1_SCK. |
| 56 | PB4 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions NJTRST, SPI3_MISO, TIM3_CH1, SPI1_MISO and I2S3ext_SD. |
| 57 | PB5 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions I2C1_SMBA, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, TIM3_CH2, SPI1_MOSI, SPI3_MOSI, DCMI_D10 and I2S3_SD. |
| 58 | PB6 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions I2C1_SCL, TIM4_CH1, CAN2_TX, DCMI_D5 and USART1_TX. |
| 59 | PB7 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions I2C1_SDA, FSMC_NL, DCMI_VSYNC, USART1_RX and TIM4_CH2. |
| 60 | BOOT0 | input | Boot-mode selection input (also listed as VPP in the pin table), with an input voltage limit of up to 5.5 V. |
| 61 | PB8 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, ETH_MII_TXD3, SDIO_D4 and DCMI_D6. |
| 62 | PB9 | bidirectional | 5 V-tolerant GPIO (FT) with alternate functions SPI2_NSS, I2S2_WS, TIM4_CH4, TIM11_CH1, I2C1_SDA, CAN1_TX, SDIO_D5 and DCMI_D7. |
| 63 | VSS | power_in | Ground reference for the device; all voltages are referenced to VSS. |
| 64 | VDD | power_in | Supply (1.8-3.6 V) for the I/O pins and the internal voltage regulator. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CKS |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| ESD voltage, human body model | VESD(HBM) | 2000 | V | T = +25 °C，符合 JESD22-A114 (class 2) | 72 | ||
| ESD voltage, human body model, VBAT pin | VESD(HBM) | 1000 | V | VBAT pin (table footnote 2) | 72 | ||
| ESD voltage, charged device model | VESD(CDM) | 500 | V | T = +25 °C，符合 ANSI/ESD (class II) | 72 | ||
| I/O injection current, all FT pins (functional susceptibility) | IINJ | -5 | mA | All FT pins, negative injection; positive injection NA | 73 | ||
| I/O injection current, other pins (functional susceptibility) | IINJ | -5 | 5 | mA | Other pins, negative/positive injection | 73 | |
| I/O BOOT0 input hysteresis | VHYS | 0.1 | V | 1.75V≤VDD≤3.6V, -40℃≤VDD≤105℃ | 73 | ||
| I/O input leakage current | Ilkg | -1 | 1 | μA | VSS ≤ VIN ≤ VDD | 74 | |
| I/O FT input leakage current | 3 | μA | VIN = 5V | 74 | |||
| Weak pull-up equivalent resistance, all pins except PA10 and PB12 | RPU | 30 | 40 | 50 | kΩ | VIN = VSS | 74 |
| Weak pull-up equivalent resistance, PA10 and PB12 | RPU | 7 | 10 | 14 | kΩ | PA10 and PB12 pins | 74 |
| Weak pull-down equivalent resistance, all pins except PA10 and PB12 | RPD | 30 | 40 | 50 | kΩ | VIN = VDD | 74 |
| Weak pull-down equivalent resistance, PA10 and PB12 | RPD | 7 | 10 | 14 | kΩ | PA10 and PB12 pins | 74 |
| GPIO sink/source current | -8 | 8 | mA | GPIOs (standard) | 74 | ||
| GPIO sink/source current, relaxed VOL/VOH | -20 | 20 | mA | Relaxed VOL/VOH | 74 | ||
| GPIO sink/source current, PC13 PC14 PC15 | -3 | 3 | mA | PC13, PC14, PC15 pins | 74 | ||
| USB OTG FS transceiver startup time | tSTARTUP | 1 | μs | Design guaranteed, not production tested | 83 | ||
| USB OTG FS operating voltage | VDD | 3 | 3.6 | V | USB OTG FS (table footnote 2 applies to CKS32F415/417 only) | 83 | |
| USB differential input sensitivity | VDI | 0.2 | V | I(USB_FS_DP/DM, USB_HS_DP/DM) | 83 | ||
| USB differential common-mode range | VCM | 0.8 | 2.5 | V | Includes VDI range | 83 | |
| USB single-ended receiver threshold | VSE | 1.3 | 2 | V | 83 | ||
| USB static output low | VOL | 0.3 | V | RL = 1.5kΩ connected to 3.6V (design guaranteed) | 83 | ||
| USB static output high | VOH | 2.8 | 3.6 | V | RL = 15kΩ connected to ground (design guaranteed) | 83 | |
| USB pull-down resistance, PA11 PA12 PB14 PB15 | RPD | 17 | 21 | 24 | kΩ | VIN = VDD | 83 |
| USB pull-down resistance, PA9 PB13 | RPD | 0.65 | 1.1 | 2 | kΩ | VIN = VDD | 83 |
| USB pull-up resistance, PA12 PB15 | RPU | 1.5 | 1.8 | 2.1 | kΩ | VIN = VSS | 83 |
| USB pull-up resistance, PA9 PB13 | RPU | 0.25 | 0.37 | 0.55 | kΩ | VIN = VSS | 83 |
| USB full-speed rise time | tr | 4 | 20 | ns | CL ≤ 50pF; 10% to 90% | 84 | |
| USB full-speed fall time | tf | 4 | 20 | ns | CL ≤ 50pF; 10% to 90% | 84 | |
| USB rise/fall time matching | trfm | 90 | 110 | % | tr / tf | 84 | |
| USB output signal crossover voltage | VCRS | 1.3 | 2 | V | Design guaranteed | 84 | |
| USB OTG HS operating voltage | VDD | 2.7 | 3.6 | V | USB OTG HS | 84 | |
| USB HS clock frequency, first transfer, 8-bit ±10% | FSTART_8BIT | 54 | 60 | 66 | MHz | 8-bit ±10% | 84 |
| USB HS clock frequency, steady state | FSTEADY | 59.97 | 60 | 60.03 | MHz | ±500ppm | 84 |
| USB HS clock duty cycle, first transfer, 8-bit ±10% | DSTEADY_8BIT | 40 | 50 | 60 | % | 8-bit ±10% | 84 |
| USB HS clock duty cycle, steady state | DSTEADY | 49.975 | 50 | 50.025 | % | ±500ppm | 84 |
| USB HS time to steady-state frequency and duty after first transition | TSTEADY | 1.4 | ms | 84 | |||
| USB HS clock startup time after SuspendM de-assertion, peripheral | TSTART_DEV | 5.6 | ms | Peripheral | 84 | ||
| ULPI control input (ULPI_DIR) setup time | tSC | 2 | ns | VDD = 2.7 V to 3.6 V, TA = -40 to 85°C | 84 | ||
| ULPI control input (ULPI_NXT) setup time | 1.5 | ns | VDD = 2.7 V to 3.6 V, TA = -40 to 85°C | 84 | |||
| ULPI control input (ULPI_DIR, ULPI_NXT) hold time | tHC | 0 | ns | VDD = 2.7 V to 3.6 V, TA = -40 to 85°C | 84 | ||
| ULPI data setup time | tSD | 2 | ns | VDD = 2.7 V to 3.6 V, TA = -40 to 85°C | 84 | ||
| ULPI data hold time | tHD | 0 | ns | VDD = 2.7 V to 3.6 V, TA = -40 to 85°C | 84 | ||
| ULPI control output (ULPI_STP) setup/hold time | tDC | 9.2 | ns | VDD = 2.7 V to 3.6 V, TA = -40 to 85°C | 85 | ||
| ULPI data valid time after clock rising edge | tDD | 10.7 | ns | VDD = 2.7 V to 3.6 V, TA = -40 to 85°C | 85 | ||
| Ethernet operating voltage | VDD | 2.7 | 3.6 | V | Ethernet DC electrical characteristics | 85 | |
| SMI MDC clock period | tMDC | 411 | 420 | 425 | ns | MDC clock (labelled 2.38MHz) | 85 |
| SMI write data valid time | Td(MDIO) | 6 | 10 | 13 | ns | 85 | |
| SMI read data setup time | tsu(MDIO) | 12 | ns | 85 | |||
| SMI read data hold time | th(MDIO) | 0 | ns | 85 | |||
| RMII receive data setup time | tsu(RXD) | 2 | ns | 86 | |||
| RMII receive data hold time | tih(RXD) | 1 | ns | 86 | |||
| RMII carrier sense setup time | tsu(CRS) | 0.5 | ns | 86 | |||
| RMII carrier sense hold time | tih(CRS) | 2 | ns | 86 | |||
| RMII transmit enable valid delay | td(TXEN) | 8 | 9.5 | 11 | ns | 86 | |
| RMII transmit data valid delay | td(TXD) | 8.5 | 10 | 11.5 | ns | 86 | |
| MII receive data setup time | tsu(RXD) | 9 | ns | 86 | |||
| MII receive data hold time | tih(RXD) | 10 | ns | 86 | |||
| MII data valid setup time | tsu(DV) | 9 | ns | 86 | |||
| MII data valid hold time | tih(DV) | 8 | ns | 86 | |||
| I/O pin capacitance | CIO | 5 | pF | 74 |
CAD (KiCad official)
- Symbol:
CKS32F405RGT6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
cks32f405rgt6-etched.step/cks32f405rgt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cks32f405rgt6.step/cks32f405rgt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CKS datasheet (123 pp, sha256
09eb7889abf142f1, retrieved 2026-10-21, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).