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CKS32F103VET6

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CKS Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercks32f103vet6factory-2.0.0extractor-text

Verified CKS32F103VET6

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier lcsc, 100 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CKS32F103VET6 · LQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 98-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: LQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-kma3i35i/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cks32f103vet6.kicad_sym✓ cks32f103vet6.kicad_mod✓ cks32f103vet6.step
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CKS32F103VET6

CKS · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

CKS32F103VET6 from CKS, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5V-tolerant (FT) I/O; alternate functions TRACECK and FSMC_A23.
2 PE3 bidirectional 5V-tolerant (FT) I/O; alternate functions TRACED0 and FSMC_A19.
3 PE4 bidirectional 5V-tolerant (FT) I/O; alternate functions TRACED1 and FSMC_A20.
4 PE5 bidirectional 5V-tolerant (FT) I/O; alternate functions TRACED2, FSMC_A21 and TIM9_CH1.
5 PE6 bidirectional 5V-tolerant (FT) I/O; alternate functions TRACED3, FSMC_A22 and TIM9_CH2.
6 VBAT power_in Backup domain supply for RTC, external 32 kHz oscillator and backup registers when VDD is off, 1.8 to 3.6 V.
7 PC13-TAMPER-RTC bidirectional Powered through a supply switch that sinks only 3 mA; as output limited to 2 MHz mode, 30 pF load, no LED-type current sourcing.
8 PC14-OSC32_IN bidirectional Powered through a supply switch limited to 3 mA; as output limited to 2 MHz mode, 30 pF load; OSC32_IN function.
9 PC15-OSC32_OUT bidirectional Powered through a supply switch limited to 3 mA; as output limited to 2 MHz mode, 30 pF load; OSC32_OUT function.
10 VSS_5 power_in Ground pin for the digital supply domain.
11 VDD_5 power_in Digital supply pin, VDD 2.0 to 3.6 V.
12 OSC_IN input External 4 to 16 MHz crystal oscillator input (HSE); 5V-tolerant port PD0 when remapped.
13 OSC_OUT output External 4 to 16 MHz crystal oscillator output (HSE).
14 NRST input Active-low reset input with internal pull-up (RPU 30 to 50 kΩ); external reset is applied here.
15 PC0 bidirectional I/O port PC0 with ADC analog input ADC123_IN10.
16 PC1 bidirectional I/O port PC1 with ADC analog input ADC123_IN11.
17 PC2 bidirectional I/O port PC2 with ADC analog input ADC123_IN12.
18 PC3 bidirectional I/O port PC3 with ADC analog input ADC123_IN13.
19 VSSA power_in Analog ground for ADC, DAC, reset block, RC oscillators and PLL; must be connected to VSS.
20 VREF- power_in ADC negative reference voltage input, present on 100-pin and larger packages.
21 VREF+ power_in ADC/DAC positive reference voltage, 2.4 V to VDDA.
22 VDDA power_in Analog supply for ADC, DAC, reset block, RC oscillators and PLL, 2.0 to 3.6 V; must be at least 2.4 V when ADC or DAC is used.
23 PA0-WKUP bidirectional I/O port PA0; WKUP wake-up input and USART2_CTS, ADC123_IN0, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR alternate functions.
24 PA1 bidirectional I/O port PA1; USART2_RTS, ADC123_IN1, TIM5_CH2 and TIM2_CH2 alternate functions.
25 PA2 bidirectional I/O port PA2; USART2_TX, TIM9_CH1, TIM5_CH3, ADC123_IN2 and TIM2_CH3 alternate functions.
26 PA3 bidirectional I/O port PA3; USART2_RX, TIM9_CH2, TIM5_CH4, ADC123_IN3 and TIM2_CH4 alternate functions.
27 VSS_4 power_in Ground pin for the digital supply domain.
28 VDD_4 power_in Digital supply pin, VDD 2.0 to 3.6 V.
29 PA4 bidirectional I/O port PA4; SPI1_NSS, USART2_CK, DAC_OUT1 and ADC12_IN4 alternate functions.
30 PA5 bidirectional I/O port PA5; SPI1_SCK, DAC_OUT2 and ADC12_IN5 alternate functions.
31 PA6 bidirectional I/O port PA6; SPI1_MISO, TIM8_BKIN, ADC12_IN6, TIM13_CH1 and TIM3_CH1 alternate functions.
32 PA7 bidirectional I/O port PA7; SPI1_MOSI, TIM8_CH1N, ADC12_IN7, TIM14_CH1 and TIM3_CH2 alternate functions.
33 PC4 bidirectional I/O port PC4 with ADC analog input ADC12_IN14.
34 PC5 bidirectional I/O port PC5 with ADC analog input ADC12_IN15.
35 PB0 bidirectional I/O port PB0; ADC12_IN8, TIM3_CH3, TIM8_CH2N and TIM1_CH2N alternate functions.
36 PB1 bidirectional I/O port PB1; ADC12_IN9, TIM3_CH4, TIM8_CH3N and TIM1_CH3N alternate functions.
37 PB2 bidirectional 5V-tolerant (FT) I/O; also BOOT1 boot-mode selection pin.
38 PE7 bidirectional 5V-tolerant (FT) I/O; FSMC_D4 and TIM1_ETR alternate functions.
39 PE8 bidirectional 5V-tolerant (FT) I/O; FSMC_D5 and TIM1_CH1N alternate functions.
40 PE9 bidirectional 5V-tolerant (FT) I/O; FSMC_D6 and TIM1_CH1 alternate functions.
41 PE10 bidirectional 5V-tolerant (FT) I/O; FSMC_D7 and TIM1_CH2N alternate functions.
42 PE11 bidirectional 5V-tolerant (FT) I/O; FSMC_D8 and TIM1_CH2 alternate functions.
43 PE12 bidirectional 5V-tolerant (FT) I/O; FSMC_D9 and TIM1_CH3N alternate functions.
44 PE13 bidirectional 5V-tolerant (FT) I/O; FSMC_D10 and TIM1_CH3 alternate functions.
45 PE14 bidirectional 5V-tolerant (FT) I/O; FSMC_D11 and TIM1_CH4 alternate functions.
46 PE15 bidirectional 5V-tolerant (FT) I/O; FSMC_D12 and TIM1_BKIN alternate functions.
47 PB10 bidirectional 5V-tolerant (FT) I/O; I2C2_SCL, USART3_TX and TIM2_CH3 alternate functions.
48 PB11 bidirectional 5V-tolerant (FT) I/O; I2C2_SDA, USART3_RX and TIM2_CH4 alternate functions.
49 VSS_1 power_in Ground pin for the digital supply domain.
50 VDD_1 power_in Digital supply pin, VDD 2.0 to 3.6 V.
51 PB12 bidirectional 5V-tolerant (FT) I/O; SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK and TIM1_BKIN alternate functions.
52 PB13 bidirectional 5V-tolerant (FT) I/O; SPI2_SCK, I2S2_CK, USART3_CTS and TIM1_CH1N alternate functions.
53 PB14 bidirectional 5V-tolerant (FT) I/O; SPI2_MISO, USART3_RTS, TIM12_CH1 and TIM1_CH2N alternate functions.
54 PB15 bidirectional 5V-tolerant (FT) I/O; SPI2_MOSI, I2S2_SD, TIM12_CH2 and TIM1_CH3N alternate functions.
55 PD8 bidirectional 5V-tolerant (FT) I/O; FSMC_D13 and USART3_TX alternate functions.
56 PD9 bidirectional 5V-tolerant (FT) I/O; FSMC_D14 and USART3_RX alternate functions.
57 PD10 bidirectional 5V-tolerant (FT) I/O; FSMC_D15 and USART3_CK alternate functions.
58 PD11 bidirectional 5V-tolerant (FT) I/O; FSMC_A16 and USART3_CTS alternate functions.
59 PD12 bidirectional 5V-tolerant (FT) I/O; FSMC_A17, TIM4_CH1 and USART3_RTS alternate functions.
60 PD13 bidirectional 5V-tolerant (FT) I/O; FSMC_A18 and TIM4_CH2 alternate functions.
61 PD14 bidirectional 5V-tolerant (FT) I/O; FSMC_D0 and TIM4_CH3 alternate functions.
62 PD15 bidirectional 5V-tolerant (FT) I/O; FSMC_D1 and TIM4_CH4 alternate functions.
63 PC6 bidirectional 5V-tolerant (FT) I/O; I2S2_MCK and TIM3_CH1 alternate functions.
64 PC7 bidirectional 5V-tolerant (FT) I/O; I2S3_MCK, TIM8_CH2, USART6_RX, SDIO_D7 and TIM3_CH2 alternate functions.
65 PC8 bidirectional 5V-tolerant (FT) I/O; TIM8_CH3, USART6_CK, SDIO_D0 and TIM3_CH3 alternate functions.
66 PC9 bidirectional 5V-tolerant (FT) I/O; TIM8_CH4, SDIO_D1 and TIM3_CH4 alternate functions.
67 PA8 bidirectional 5V-tolerant (FT) I/O; USART1_CK, TIM1_CH1 and MCO alternate functions.
68 PA9 bidirectional 5V-tolerant (FT) I/O; USART1_TX and TIM1_CH2 alternate functions.
69 PA10 bidirectional 5V-tolerant (FT) I/O; USART1_RX and TIM1_CH3 alternate functions.
70 PA11 bidirectional 5V-tolerant (FT) I/O; USART1_CTS, USBDM, CAN_RX and TIM1_CH4 alternate functions.
71 PA12 bidirectional 5V-tolerant (FT) I/O; USART1_RTS, USBDP, CAN_TX and TIM1_ETR alternate functions.
72 PA13 bidirectional 5V-tolerant (FT) I/O; JTMS/SWDIO debug function after reset.
73 NC unconnected Printed as 未连接 (not connected) in the LQFP100 column of the pin definition table.
74 VSS_2 power_in Ground pin for the digital supply domain.
75 VDD_2 power_in Digital supply pin, VDD 2.0 to 3.6 V.
76 PA14 bidirectional 5V-tolerant (FT) I/O; JTCK/SWCLK debug function after reset.
77 PA15 bidirectional 5V-tolerant (FT) I/O; JTDI debug function after reset; SPI3_NSS, I2S3_WS and TIM2_CH1_ETR alternate functions.
78 PC10 bidirectional 5V-tolerant (FT) I/O; USART4_TX, SDIO_D2 and USART3_TX alternate functions.
79 PC11 bidirectional 5V-tolerant (FT) I/O; USART4_RX, SDIO_D3 and USART3_RX alternate functions.
80 PC12 bidirectional 5V-tolerant (FT) I/O; USART5_TX, SDIO_CK and USART3_CK alternate functions.
81 PD0 bidirectional 5V-tolerant (FT) I/O; fixed function OSC_IN on this package, with FSMC_D2 and CAN_RX alternate functions.
82 PD1 bidirectional 5V-tolerant (FT) I/O; fixed function OSC_OUT on this package, with FSMC_D3 and CAN_TX alternate functions.
83 PD2 bidirectional 5V-tolerant (FT) I/O; TIM3_ETR, USART5_RX and SDIO_CMD alternate functions.
84 PD3 bidirectional 5V-tolerant (FT) I/O; FSMC_CLK and USART2_CTS alternate functions.
85 PD4 bidirectional 5V-tolerant (FT) I/O; FSMC_NOE and USART2_RTS alternate functions.
86 PD5 bidirectional 5V-tolerant (FT) I/O; FSMC_NWE and USART2_TX alternate functions.
87 PD6 bidirectional 5V-tolerant (FT) I/O; FSMC_NWAIT and USART2_RX alternate functions.
88 PD7 bidirectional 5V-tolerant (FT) I/O; FSMC_NE1/FSMC_NCE2 and USART2_CK alternate functions.
89 PB3 bidirectional 5V-tolerant (FT) I/O; JTDO debug function after reset; SPI3_SCK, I2S3_CK, TRACESWO, TIM2_CH2 and SPI1_SCK alternate functions.
90 PB4 bidirectional 5V-tolerant (FT) I/O; NJTRST debug function after reset; SPI3_MISO, TIM3_CH1 and SPI1_MISO alternate functions.
91 PB5 bidirectional I/O port PB5; I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2 and SPI1_MOSI alternate functions.
92 PB6 bidirectional 5V-tolerant (FT) I/O; I2C1_SCL, USART1_TX and TIM4_CH1 alternate functions.
93 PB7 bidirectional 5V-tolerant (FT) I/O; I2C1_SDA, FSMC_NADV, TIM4_CH2 and USART1_RX alternate functions.
94 BOOT0 input Boot mode selection input (BOOT0) used at startup to select the boot source.
95 PB8 bidirectional 5V-tolerant (FT) I/O; TIM4_CH3, TIM10_CH1, SDIO_D4, I2C1_SCL and CAN_RX alternate functions.
96 PB9 bidirectional 5V-tolerant (FT) I/O; TIM4_CH4, TIM11_CH1, SDIO_D5, I2C1_SDA and CAN_TX alternate functions.
97 PE0 bidirectional 5V-tolerant (FT) I/O; TIM4_ETR and FSMC_NBL0 alternate functions.
98 PE1 bidirectional 5V-tolerant (FT) I/O; FSMC_NBL1 alternate function.
99 VSS_3 power_in Ground pin for the digital supply domain.
100 VDD_3 power_in Digital supply pin, VDD 2.0 to 3.6 V; the 4.7 µF decoupling capacitor in the power scheme must connect to VDD3.

Key specifications

Parameter Value
Manufacturer CKS
Package LQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
USB operating voltage VDD 3 3.6 V 83
Static output high level VOH 2.8 3.6 V 15kΩ RL to VSS 83
Static output low level VOL 0.3 V 1.5kΩ RL to 3.6V 83
Differential common mode range VCM 0.8 2.5 V Includes VDI range 83
Single-ended receiver threshold VSE 1.3 2 V 83
USB transceiver startup time tSTARTUP 1 μs Guaranteed by design, not tested in production 83
Rise time (data signal, 10% to 90%) tr 4 20 ns CL ≤ 50pF 84
Fall time (data signal, 10% to 90%) tf 4 20 ns CL ≤ 50pF 84
Rise/fall time matching trfm 90 110 % tr / tf 84
Output signal crossover voltage VCRS 1.3 2 V 84
ADC supply voltage VDDA 2.4 3.6 V 84
Positive reference voltage VREF+ 2.4 V 84
Current on VREF input pin IVREF 160 220 μA 84
ADC clock frequency fADC 0.6 14 MHz 84
Sampling rate fS 0.05 1 MHz 84
External trigger frequency fTRIG 823 kHz fADC=14MHz 84
External trigger frequency fTRIG 17 1/fADC 84
Conversion voltage range VAIN 0 V VSSA or VREF- connected to ground 84
Sampling switch resistance RADC 1 kΩ 84
Sampling time tS 0.107 17.1 μs fADC=14MHz 85
Sampling time tS 1.5 239.5 1/fADC 85
ADC power-up time tSTAB 0 0 1 μs 85
Total conversion time (including sampling time) tCONV 1 18 μs fADC=14MHz 85
Total conversion time (including sampling time) tCONV 14 252 1/fADC Sampling tS + successive approximation 12.5 85
Maximum external input impedance RAIN RAIN 1.2 kΩ fADC=14MHz; TS=1.5 cycles (0.11 μs) 85
Maximum external input impedance RAIN RAIN 10 kΩ fADC=14MHz; TS=7.5 cycles (0.54 μs) 85
Maximum external input impedance RAIN RAIN 19 kΩ fADC=14MHz; TS=13.5 cycles (0.96 μs) 85
Maximum external input impedance RAIN RAIN 41 kΩ fADC=14MHz; TS=28.5 cycles (2.04 μs) 85
Maximum external input impedance RAIN RAIN 60 kΩ fADC=14MHz; TS=41.5 cycles (2.96 μs) 85
Maximum external input impedance RAIN RAIN 80 kΩ fADC=14MHz; TS=55.5 cycles (3.96 μs) 85
Maximum external input impedance RAIN RAIN 104 kΩ fADC=14MHz; TS=71.5 cycles (5.11 μs) 85
Maximum external input impedance RAIN RAIN 350 kΩ fADC=14MHz; TS=239.5 cycles (17.1 μs) 85
ADC total unadjusted error ET -2 1.3 2 LSB fPCLK2=56MHz; fADC=14MHz; RAIN<10kΩ; VDDA=3~3.6V; TA=25°C; measured after ADC calibration; VREF+=VDDA 85
ADC offset error EO -1.5 1 1.5 LSB fPCLK2=56MHz; fADC=14MHz; RAIN<10kΩ; VDDA=3~3.6V; TA=25°C; measured after ADC calibration; VREF+=VDDA 85
ADC gain error EG -1.5 0.5 1.5 LSB fPCLK2=56MHz; fADC=14MHz; RAIN<10kΩ; VDDA=3~3.6V; TA=25°C; measured after ADC calibration; VREF+=VDDA 85
ADC differential non-linearity error ED -1 0.7 1 LSB fPCLK2=56MHz; fADC=14MHz; RAIN<10kΩ; VDDA=3~3.6V; TA=25°C; measured after ADC calibration; VREF+=VDDA 85
ADC integral non-linearity error EL -1.5 0.8 1.5 LSB fPCLK2=56MHz; fADC=14MHz; RAIN<10kΩ; VDDA=3~3.6V; TA=25°C; measured after ADC calibration; VREF+=VDDA 85
SD/MMC clock frequency in data transfer mode fPP 0 MHz CL ≤ 30pF; maximum printed as TBD 82

CAD (KiCad official)

  • Symbol: CKS32F103VET6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: cks32f103vet6-etched.step / cks32f103vet6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cks32f103vet6.step / cks32f103vet6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CKS datasheet (98 pp, sha256 3b7626fd9350b985, retrieved 2026-11-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF