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CKS32F103VCT6
Public Made by Adomby adom
CKS Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownCKS32F103VCT6
CKS · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
CKS32F103VCT6 from CKS, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V tolerant (FT) I/O; alternate functions TRACECK and FSMC_A23. |
| 2 | PE3 | bidirectional | 5 V tolerant (FT) I/O; alternate functions TRACED0 and FSMC_A19. |
| 3 | PE4 | bidirectional | 5 V tolerant (FT) I/O; alternate functions TRACED1 and FSMC_A20. |
| 4 | PE5 | bidirectional | 5 V tolerant (FT) I/O; alternate functions TRACED2, FSMC_A21 and TIM9_CH1. |
| 5 | PE6 | bidirectional | 5 V tolerant (FT) I/O; alternate functions TRACED3, FSMC_A22 and TIM9_CH2. |
| 6 | VBAT | power_in | Backup supply 1.8 V to 3.6 V that powers the RTC, the external 32 kHz oscillator and the backup registers when VDD is off. |
| 7 | PC13-TAMPER-RTC | bidirectional | Powered through a power switch that sinks only about 3 mA; as an output it is limited to 2 MHz mode with at most 30 pF load and cannot source current such as driving an LED. Alternate function TAMPER-RTC. |
| 8 | PC14-OSC32_IN | bidirectional | Powered through the same limited power switch (about 3 mA); as an output it is limited to 2 MHz mode, 30 pF maximum load and no current sourcing. Alternate function OSC32_IN. |
| 9 | PC15-OSC32_OUT | bidirectional | Powered through the same limited power switch (about 3 mA); as an output it is limited to 2 MHz mode, 30 pF maximum load and no current sourcing. Alternate function OSC32_OUT. |
| 10 | VSS_5 | power_in | Ground pin; all VSS pins must be connected to the ground system. |
| 11 | VDD_5 | power_in | Digital supply pin for I/O and the internal regulator, 2.0 V to 3.6 V. |
| 12 | OSC_IN | input | HSE oscillator input for a 4 to 16 MHz crystal or resonator. |
| 13 | OSC_OUT | output | HSE oscillator output for a 4 to 16 MHz crystal or resonator. |
| 14 | NRST | bidirectional | Active-low reset pin with a non-disconnectable pull-up of 30 to 50 kΩ; input low level maximum 0.8 V and input high level minimum 2 V. |
| 15 | PC0 | bidirectional | General-purpose I/O; alternate function ADC123_IN10. |
| 16 | PC1 | bidirectional | General-purpose I/O; alternate function ADC123_IN11. |
| 17 | PC2 | bidirectional | General-purpose I/O; alternate function ADC123_IN12. |
| 18 | PC3 | bidirectional | General-purpose I/O; alternate function ADC123_IN13. |
| 19 | VSSA | power_in | Analog ground for ADC, DAC, reset block, RC oscillators and PLL; must be connected to VSS. |
| 20 | VREF- | power_in | Negative ADC reference voltage input, present on 100-pin and larger packages. |
| 21 | VREF+ | power_in | Positive ADC and DAC reference voltage input, 2.4 V up to VDDA, present on 100-pin and larger packages. |
| 22 | VDDA | power_in | Analog supply for ADC, DAC, reset block, RC oscillators and PLL, 2.0 V to 3.6 V; must be at least 2.4 V when the ADC or DAC is used and must be connected to VDD. |
| 23 | PA0-WKUP | bidirectional | General-purpose I/O; WKUP wake-up input for standby and stop modes; alternate functions USART2_CTS, ADC123_IN0, TIM2_CH1_ETR, TIM5_CH1 and TIM8_ETR. |
| 24 | PA1 | bidirectional | General-purpose I/O; alternate functions USART2_RTS, ADC123_IN1, TIM5_CH2 and TIM2_CH2. |
| 25 | PA2 | bidirectional | General-purpose I/O; alternate functions USART2_TX, TIM9_CH1, TIM5_CH3, ADC123_IN2 and TIM2_CH3. |
| 26 | PA3 | bidirectional | General-purpose I/O; alternate functions USART2_RX, TIM9_CH2, TIM5_CH4, ADC123_IN3 and TIM2_CH4. |
| 27 | VSS_4 | power_in | Ground pin; all VSS pins must be connected to the ground system. |
| 28 | VDD_4 | power_in | Digital supply pin for I/O and the internal regulator, 2.0 V to 3.6 V. |
| 29 | PA4 | bidirectional | General-purpose I/O; alternate functions SPI1_NSS, USART2_CK, DAC_OUT1 and ADC12_IN4. |
| 30 | PA5 | bidirectional | General-purpose I/O; alternate functions SPI1_SCK, DAC_OUT2 and ADC12_IN5. |
| 31 | PA6 | bidirectional | General-purpose I/O; alternate functions SPI1_MISO, TIM8_BKIN, ADC12_IN6, TIM13_CH1, TIM3_CH1 and TIM1_BKIN. |
| 32 | PA7 | bidirectional | General-purpose I/O; alternate functions SPI1_MOSI, TIM8_CH1N, ADC12_IN7, TIM14_CH1, TIM3_CH2 and TIM1_CH1N. |
| 33 | PC4 | bidirectional | General-purpose I/O; alternate function ADC12_IN14. |
| 34 | PC5 | bidirectional | General-purpose I/O; alternate function ADC12_IN15. |
| 35 | PB0 | bidirectional | General-purpose I/O; alternate functions ADC12_IN8, TIM3_CH3, TIM8_CH2N and TIM1_CH2N. |
| 36 | PB1 | bidirectional | General-purpose I/O; alternate functions ADC12_IN9, TIM3_CH4, TIM8_CH3N and TIM1_CH3N. |
| 37 | PB2/BOOT1 | bidirectional | 5 V tolerant (FT) I/O; also used as the BOOT1 boot-mode configuration pin. |
| 38 | PE7 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D4 and TIM1_ETR. |
| 39 | PE8 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D5 and TIM1_CH1N. |
| 40 | PE9 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D6 and TIM1_CH1. |
| 41 | PE10 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D7 and TIM1_CH2N. |
| 42 | PE11 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D8 and TIM1_CH2. |
| 43 | PE12 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D9 and TIM1_CH3N. |
| 44 | PE13 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D10 and TIM1_CH3. |
| 45 | PE14 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D11 and TIM1_CH4. |
| 46 | PE15 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D12 and TIM1_BKIN. |
| 47 | PB10 | bidirectional | 5 V tolerant (FT) I/O; alternate functions I2C2_SCL, USART3_TX and TIM2_CH3. |
| 48 | PB11 | bidirectional | 5 V tolerant (FT) I/O; alternate functions I2C2_SDA, USART3_RX and TIM2_CH4. |
| 49 | VSS_1 | power_in | Ground pin; all VSS pins must be connected to the ground system. |
| 50 | VDD_1 | power_in | Digital supply pin for I/O and the internal regulator, 2.0 V to 3.6 V. |
| 51 | PB12 | bidirectional | 5 V tolerant (FT) I/O; alternate functions SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK and TIM1_BKIN. |
| 52 | PB13 | bidirectional | 5 V tolerant (FT) I/O; alternate functions SPI2_SCK, I2S2_CK, USART3_CTS and TIM1_CH1N. |
| 53 | PB14 | bidirectional | 5 V tolerant (FT) I/O; alternate functions SPI2_MISO, USART3_RTS, TIM12_CH1 and TIM1_CH2N. |
| 54 | PB15 | bidirectional | 5 V tolerant (FT) I/O; alternate functions SPI2_MOSI, I2S2_SD, TIM12_CH2 and TIM1_CH3N. |
| 55 | PD8 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D13 and USART3_TX. |
| 56 | PD9 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D14 and USART3_RX. |
| 57 | PD10 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D15 and USART3_CK. |
| 58 | PD11 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_A16 and USART3_CTS. |
| 59 | PD12 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_A17, TIM4_CH1 and USART3_RTS. |
| 60 | PD13 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_A18 and TIM4_CH2. |
| 61 | PD14 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D0 and TIM4_CH3. |
| 62 | PD15 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_D1 and TIM4_CH4. |
| 63 | PC6 | bidirectional | 5 V tolerant (FT) I/O; alternate functions I2S2_MCK, TIM3_CH1, TIM8_CH1, USART6_TX and SDIO_D6. |
| 64 | PC7 | bidirectional | 5 V tolerant (FT) I/O; alternate functions I2S3_MCK, TIM8_CH2, USART6_RX, SDIO_D7 and TIM3_CH2. |
| 65 | PC8 | bidirectional | 5 V tolerant (FT) I/O; alternate functions TIM8_CH3, USART6_CK, SDIO_D0 and TIM3_CH3. |
| 66 | PC9 | bidirectional | 5 V tolerant (FT) I/O; alternate functions TIM8_CH4, SDIO_D1 and TIM3_CH4. |
| 67 | PA8 | bidirectional | 5 V tolerant (FT) I/O; alternate functions USART1_CK, TIM1_CH1 and MCO. |
| 68 | PA9 | bidirectional | 5 V tolerant (FT) I/O; alternate functions USART1_TX and TIM1_CH2. |
| 69 | PA10 | bidirectional | 5 V tolerant (FT) I/O; alternate functions USART1_RX and TIM1_CH3. |
| 70 | PA11 | bidirectional | 5 V tolerant (FT) I/O; alternate functions USART1_CTS, USBDM, CAN_RX and TIM1_CH4. |
| 71 | PA12 | bidirectional | 5 V tolerant (FT) I/O; alternate functions USART1_RTS, USBDP, CAN_TX and TIM1_ETR. |
| 72 | PA13 | bidirectional | 5 V tolerant (FT) I/O; reset-state function JTMS/SWDIO (serial wire debug data). |
| 73 | NC | unconnected | Listed as 未连接 (not connected) in the LQFP100 column of the pin definition table. |
| 74 | VSS_2 | power_in | Ground pin; all VSS pins must be connected to the ground system. |
| 75 | VDD_2 | power_in | Digital supply pin for I/O and the internal regulator, 2.0 V to 3.6 V. |
| 76 | PA14 | bidirectional | 5 V tolerant (FT) I/O; reset-state function JTCK/SWCLK (serial wire debug clock). |
| 77 | PA15 | bidirectional | 5 V tolerant (FT) I/O; reset-state function JTDI; alternate functions SPI3_NSS, I2S3_WS, TIM2_CH1_ETR and SPI1_NSS. |
| 78 | PC10 | bidirectional | 5 V tolerant (FT) I/O; alternate functions USART4_TX, SDIO_D2 and USART3_TX. |
| 79 | PC11 | bidirectional | 5 V tolerant (FT) I/O; alternate functions USART4_RX, SDIO_D3 and USART3_RX. |
| 80 | PC12 | bidirectional | 5 V tolerant (FT) I/O; alternate functions USART5_TX, SDIO_CK and USART3_CK. |
| 81 | PD0 | bidirectional | 5 V tolerant (FT) I/O; on LQFP100 this is a native pin, alternate functions OSC_IN, FSMC_D2 and CAN_RX. |
| 82 | PD1 | bidirectional | 5 V tolerant (FT) I/O; on LQFP100 this is a native pin, alternate functions OSC_OUT, FSMC_D3 and CAN_TX. |
| 83 | PD2 | bidirectional | 5 V tolerant (FT) I/O; alternate functions TIM3_ETR, USART5_RX and SDIO_CMD. |
| 84 | PD3 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_CLK and USART2_CTS. |
| 85 | PD4 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_NOE and USART2_RTS. |
| 86 | PD5 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_NWE and USART2_TX. |
| 87 | PD6 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_NWAIT and USART2_RX. |
| 88 | PD7 | bidirectional | 5 V tolerant (FT) I/O; alternate functions FSMC_NE1/FSMC_NCE2 and USART2_CK. |
| 89 | PB3 | bidirectional | 5 V tolerant (FT) I/O; reset-state function JTDO; alternate functions SPI3_SCK, I2S3_CK, TRACESWO, TIM2_CH2 and SPI1_SCK. |
| 90 | PB4 | bidirectional | 5 V tolerant (FT) I/O; reset-state function NJTRST; alternate functions SPI3_MISO, TIM3_CH1 and SPI1_MISO. |
| 91 | PB5 | bidirectional | I/O; alternate functions I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2 and SPI1_MOSI. |
| 92 | PB6 | bidirectional | 5 V tolerant (FT) I/O; alternate functions I2C1_SCL, USART1_TX and TIM4_CH1. |
| 93 | PB7 | bidirectional | 5 V tolerant (FT) I/O; alternate functions I2C1_SDA, FSMC_NADV, TIM4_CH2 and USART1_RX. |
| 94 | BOOT0 | input | Boot mode selection input that selects flash, system memory or internal SRAM boot at startup. |
| 95 | PB8 | bidirectional | 5 V tolerant (FT) I/O; alternate functions TIM4_CH3, TIM10_CH1, SDIO_D4, I2C1_SCL and CAN_RX. |
| 96 | PB9 | bidirectional | 5 V tolerant (FT) I/O; alternate functions TIM4_CH4, TIM11_CH1, SDIO_D5, I2C1_SDA and CAN_TX. |
| 97 | PE0 | bidirectional | 5 V tolerant (FT) I/O; alternate functions TIM4_ETR and FSMC_NBL0. |
| 98 | PE1 | bidirectional | 5 V tolerant (FT) I/O; alternate function FSMC_NBL1. |
| 99 | VSS_3 | power_in | Ground pin; all VSS pins must be connected to the ground system. |
| 100 | VDD_3 | power_in | Digital supply pin for I/O and the internal regulator, 2.0 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CKS |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (supply and I/O pins) | 2 | 3.6 | V | Supply and I/O pins (features list) | 1 | ||
| USB operating voltage | VDD | 3 | 3.6 | V | 83 | ||
| Analog supply voltage | VDDA | 2.4 | 3.6 | V | 84 | ||
| Positive reference voltage | VREF+ | 2.4 | V | 84 | |||
| Current on VREF input pin | IVREF | 160 | 220 | μA | 84 | ||
| ADC clock frequency | fADC | 0.6 | 14 | MHz | 84 | ||
| Sampling rate | fS | 0.05 | 1 | MHz | 84 | ||
| External trigger frequency | fTRIG | 823 | kHz | fADC=14MHz | 84 | ||
| External trigger frequency (cycles) | fTRIG | 17 | 1/fADC | 84 | |||
| Conversion voltage range | VAIN | 0 | V | VSSA or VREF- connected to ground | 84 | ||
| Sampling switch resistance | RADC | 1 | kΩ | 84 | |||
| Sampling time | tS | 0.107 | 17.1 | μs | fADC=14MHz | 85 | |
| Sampling time (cycles) | tS | 1.5 | 239.5 | 1/fADC | 85 | ||
| ADC power-up time | tSTAB | 0 | 0 | 1 | μs | 85 | |
| Total conversion time (including sampling) | tCONV | 1 | 18 | μs | fADC=14MHz | 85 | |
| Total conversion time (cycles) | tCONV | 14 | 252 | 1/fADC | tS sampling + 12.5 successive approximation | 85 | |
| Total unadjusted error (ET) | ET | -2 | 1.3 | 2 | LSB | fPCLK2=56 MHz, fADC=14 MHz, RAIN<10 kΩ, VDDA=3~3.6V, TA=25 °C, VREF+=VDDA, after calibration | 85 |
| Offset error (EO) | EO | -1.5 | 1 | 1.5 | LSB | 85 | |
| Gain error (EG) | EG | -1.5 | 0.5 | 1.5 | LSB | 85 | |
| Differential linearity error (ED) | ED | -1 | 0.7 | 1 | LSB | 85 | |
| Integral linearity error (EL) | EL | -1.5 | 0.8 | 1.5 | LSB | 85 | |
| USB transceiver startup time | tSTARTUP | 1 | μs | 83 | |||
| USB differential input sensitivity | VDI | 0.2 | V | I(USBDP,USBDM) | 83 | ||
| USB differential common-mode range | VCM | 0.8 | 2.5 | V | includes VDI range | 83 | |
| USB single-ended receiver threshold | VSE | 1.3 | 2 | V | 83 | ||
| Static output low level | VOL | 0.3 | V | 1.5kΩ RL to 3.6V | 83 | ||
| Static output high level | VOH | 2.8 | 3.6 | V | 15kΩ RL to VSS | 83 | |
| USB data rise time | tr | 4 | 20 | ns | CL ≤ 50pF | 84 | |
| USB data fall time | tf | 4 | 20 | ns | CL ≤ 50pF | 84 | |
| USB rise/fall time matching | trfm | 90 | 110 | % | tr/tf | 84 | |
| Output signal crossover voltage | VCRS | 1.3 | 2 | V | 84 |
CAD (KiCad official)
- Symbol:
CKS32F103VCT6 - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
cks32f103vct6-etched.step/cks32f103vct6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cks32f103vct6.step/cks32f103vct6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CKS datasheet (98 pp, sha256
3b7626fd9350b985, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).