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CKS32F103VBT6

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CKS Other Processors and Microcontrollers (MCUs), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscks32f103vbt6factory-2.0.0extractor-text
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Contents

README

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CKS32F103VBT6

CKS · Other Processors and Microcontrollers (MCUs) · LQFP-100(14x14)

CKS32F103VBT6 from CKS, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional I/O port PE2 (5 V tolerant, FT) with alternate function TRACECK.
2 PE3 bidirectional I/O port PE3 (5 V tolerant, FT) with alternate function TRACED0.
3 PE4 bidirectional I/O port PE4 (5 V tolerant, FT) with alternate function TRACED1.
4 PE5 bidirectional I/O port PE5 (5 V tolerant, FT) with alternate function TRACED2.
5 PE6 bidirectional I/O port PE6 (5 V tolerant, FT) with alternate function TRACED3.
6 VBAT power_in Backup supply of 1.8 to 3.6 V that powers the RTC, the 32 kHz oscillator and backup registers when VDD is switched off.
7 PC13-TAMPER-RTC bidirectional I/O port PC13 with TAMPER-RTC function, supplied through a power switch that can sink only 3 mA, so as an output it is limited to 2 MHz mode, 30 pF maximum load and no current sourcing such as LED drive.
8 PC14-OSC32_IN bidirectional I/O port PC14 with OSC32_IN function, supplied through the same 3 mA power switch as PC13, so as an output it is limited to 2 MHz mode, 30 pF maximum load and no current sourcing.
9 PC15-OSC32_OUT bidirectional I/O port PC15 with OSC32_OUT function, supplied through the same 3 mA power switch as PC13, so as an output it is limited to 2 MHz mode, 30 pF maximum load and no current sourcing.
10 VSS_5 power_in Digital ground pin; all VDD and VSS pins must always be connected to the supply within the allowed range.
11 VDD_5 power_in Digital supply pin for I/O and the internal regulator, specified at 2.0 to 3.6 V.
12 OSC_IN input High-speed external oscillator input for a 4 to 16 MHz crystal or resonator; the datasheet also specifies an external user clock of 7.95 to 8.05 MHz (8 MHz nominal) on this pin.
13 OSC_OUT output High-speed external oscillator output that drives the 4 to 16 MHz crystal or resonator connected between OSC_IN and OSC_OUT.
14 NRST bidirectional Active-low reset pin with an internal pull-up of 30 to 50 kΩ; input low level must be 0.8 V maximum and pulses shorter than 100 ns are filtered.
15 PC0 bidirectional Standard I/O port PC0 (not 5 V tolerant) with ADC12_IN10 analog input.
16 PC1 bidirectional Standard I/O port PC1 (not 5 V tolerant) with ADC12_IN11 analog input.
17 PC2 bidirectional Standard I/O port PC2 (not 5 V tolerant) with ADC12_IN12 analog input.
18 PC3 bidirectional Standard I/O port PC3 (not 5 V tolerant) with ADC12_IN13 analog input.
19 VSSA power_in Analog ground for the ADC, reset block, RC oscillators and PLL, to be connected to VSS.
20 VREF- power_in ADC negative reference voltage input, an external pin on LQFP100 (internally tied to VSSA on QFN36, LQFP48 and LQFP64).
21 VREF+ power_in ADC positive reference voltage input, specified from 2.4 V up to VDDA (internally tied to VDDA on QFN36, LQFP48 and LQFP64).
22 VDDA power_in Analog supply for the ADC, reset block, RC oscillators and PLL, specified at 2.0 to 3.6 V, with a minimum of 2.4 V when the ADC is used, and it must be connected to VDD.
23 PA0-WKUP bidirectional Standard I/O port PA0 with WKUP wake-up function, USART2_CTS, ADC12_IN0 and TIM2_CH1_ETR alternate functions.
24 PA1 bidirectional Standard I/O port PA1 with USART2_RTS, ADC12_IN1 and TIM2_CH2 alternate functions.
25 PA2 bidirectional Standard I/O port PA2 with USART2_TX, ADC12_IN2 and TIM2_CH3 alternate functions.
26 PA3 bidirectional Standard I/O port PA3 with USART2_RX, ADC12_IN3 and TIM2_CH4 alternate functions.
27 VSS_4 power_in Digital ground pin; all VDD and VSS pins must always be connected to the supply within the allowed range.
28 VDD_4 power_in Digital supply pin for I/O and the internal regulator, specified at 2.0 to 3.6 V.
29 PA4 bidirectional Standard I/O port PA4 with SPI1_NSS, USART2_CK and ADC12_IN4 alternate functions.
30 PA5 bidirectional Standard I/O port PA5 with SPI1_SCK and ADC12_IN5 alternate functions.
31 PA6 bidirectional Standard I/O port PA6 with SPI1_MISO, ADC12_IN6, TIM3_CH1 and TIM1_BKIN alternate functions.
32 PA7 bidirectional Standard I/O port PA7 with SPI1_MOSI, ADC12_IN7, TIM3_CH2 and TIMI_CHIN alternate functions (name as printed in the datasheet).
33 PC4 bidirectional Standard I/O port PC4 (not 5 V tolerant) with ADC12_IN14 analog input.
34 PC5 bidirectional Standard I/O port PC5 (not 5 V tolerant) with ADC12_IN15 analog input.
35 PB0 bidirectional Standard I/O port PB0 with ADC12_IN8, TIM3_CH3 and TIM1_CH2N alternate functions.
36 PB1 bidirectional Standard I/O port PB1 with ADC12_IN9, TIM3_CH4 and TIM1_CH3N alternate functions.
37 PB2 bidirectional 5 V tolerant I/O port PB2 (FT) that is shared with the BOOT1 boot-mode function.
38 PE7 bidirectional 5 V tolerant I/O port PE7 (FT) with alternate function TIM1_ETR.
39 PE8 bidirectional 5 V tolerant I/O port PE8 (FT) with alternate function TIM1_CH1N.
40 PE9 bidirectional 5 V tolerant I/O port PE9 (FT) with alternate function TIM1_CH1.
41 PE10 bidirectional 5 V tolerant I/O port PE10 (FT) with alternate function TIM1_CH2N.
42 PE11 bidirectional 5 V tolerant I/O port PE11 (FT) with alternate function TIM1_CH2.
43 PE12 bidirectional 5 V tolerant I/O port PE12 (FT) with alternate function TIM1_CH3N.
44 PE13 bidirectional 5 V tolerant I/O port PE13 (FT) with alternate function TIM1_CH3.
45 PE14 bidirectional 5 V tolerant I/O port PE14 (FT) with alternate function TIM1_CH4.
46 PE15 bidirectional 5 V tolerant I/O port PE15 (FT) with alternate function TIM1_BKIN.
47 PB10 bidirectional 5 V tolerant I/O port PB10 (FT) with I2C2_SCL, USART3_TX and TIM2_CH3 alternate functions.
48 PB11 bidirectional 5 V tolerant I/O port PB11 (FT) with I2C2_SDA, USART3_RX and TIM2_CH4 alternate functions.
49 VSS_1 power_in Digital ground pin; all VDD and VSS pins must always be connected to the supply within the allowed range.
50 VDD_1 power_in Digital supply pin for I/O and the internal regulator, specified at 2.0 to 3.6 V.
51 PB12 bidirectional 5 V tolerant I/O port PB12 (FT) with SPI2_NSS, I2C2_SMBAI, USART3_CK and TIM1_BKIN alternate functions.
52 PB13 bidirectional 5 V tolerant I/O port PB13 (FT) with SPI2_SCK, USART3_CTS and TIM1_CH1N alternate functions.
53 PB14 bidirectional 5 V tolerant I/O port PB14 (FT) with SPI2_MISO, USART3_RTS and TIM1_CH2N alternate functions.
54 PB15 bidirectional 5 V tolerant I/O port PB15 (FT) with SPI2_MOSI and TIM1_CH3N alternate functions.
55 PD8 bidirectional 5 V tolerant I/O port PD8 (FT) with alternate function USART3_TX.
56 PD9 bidirectional 5 V tolerant I/O port PD9 (FT) with alternate function USART3_RX.
57 PD10 bidirectional 5 V tolerant I/O port PD10 (FT) with alternate function USART3_CK.
58 PD11 bidirectional 5 V tolerant I/O port PD11 (FT) with alternate function USART3_CTS.
59 PD12 bidirectional 5 V tolerant I/O port PD12 (FT) with TIM4_CH1 and USART3_RTS alternate functions.
60 PD13 bidirectional 5 V tolerant I/O port PD13 (FT) with alternate function TIM4_CH2.
61 PD14 bidirectional 5 V tolerant I/O port PD14 (FT) with alternate function TIM4_CH3.
62 PD15 bidirectional 5 V tolerant I/O port PD15 (FT) with alternate function TIM4_CH4.
63 PC6 bidirectional 5 V tolerant I/O port PC6 (FT) with alternate function TIM3_CH1.
64 PC7 bidirectional 5 V tolerant I/O port PC7 (FT) with alternate function TIM3_CH2.
65 PC8 bidirectional 5 V tolerant I/O port PC8 (FT) with alternate function TIM3_CH3.
66 PC9 bidirectional 5 V tolerant I/O port PC9 (FT) with alternate function TIM3_CH4.
67 PA8 bidirectional 5 V tolerant I/O port PA8 (FT) with USART1_CK, TIM1_CH1 and MCO alternate functions.
68 PA9 bidirectional 5 V tolerant I/O port PA9 (FT) with USART1_TX and TIM1_CH2 alternate functions.
69 PA10 bidirectional 5 V tolerant I/O port PA10 (FT) with USART1_RX and TIM1_CH3 alternate functions.
70 PA11 bidirectional 5 V tolerant I/O port PA11 (FT) with USART1_CTS, USBDM, CANRX and TIM1_CH4 alternate functions.
71 PA12 bidirectional 5 V tolerant I/O port PA12 (FT) with USART1_RTS, USBDP, CANTX and TIM1_ETR alternate functions.
72 PA13 bidirectional 5 V tolerant I/O port PA13 (FT) whose main function is JTMS/SWDIO serial-wire debug.
73 NC unconnected Pin marked 未连接 (not connected) in the LQFP100 pin table.
74 VSS_2 power_in Digital ground pin; all VDD and VSS pins must always be connected to the supply within the allowed range.
75 VDD_2 power_in Digital supply pin for I/O and the internal regulator, specified at 2.0 to 3.6 V.
76 PA14 bidirectional 5 V tolerant I/O port PA14 (FT) whose main function is JTCK/SWCLK serial-wire debug clock.
77 PA15 bidirectional 5 V tolerant I/O port PA15 (FT) whose main function is JTDI, with TIM2_CH1_ETR alternate function and PA15/SPI1_NSS remap.
78 PC10 bidirectional 5 V tolerant I/O port PC10 (FT) with alternate function USART3_TX.
79 PC11 bidirectional 5 V tolerant I/O port PC11 (FT) with alternate function USART3_RX.
80 PC12 bidirectional 5 V tolerant I/O port PC12 (FT) with alternate function USART3_CK.
81 PD0 bidirectional 5 V tolerant I/O port PD0 (FT), inherent on LQFP100 with CANRX alternate function; the table also lists OSC_IN for this pin row.
82 PD1 bidirectional 5 V tolerant I/O port PD1 (FT) with CANTX alternate function; in output mode it can only be configured to 50 MHz.
83 PD2 bidirectional 5 V tolerant I/O port PD2 (FT) with alternate function TIM3_ETR.
84 PD3 bidirectional 5 V tolerant I/O port PD3 (FT) with alternate function USART2_CTS.
85 PD4 bidirectional 5 V tolerant I/O port PD4 (FT) with alternate function USART2_RTS.
86 PD5 bidirectional 5 V tolerant I/O port PD5 (FT) with alternate function USART2_TX.
87 PD6 bidirectional 5 V tolerant I/O port PD6 (FT) with alternate function USART2_RX.
88 PD7 bidirectional 5 V tolerant I/O port PD7 (FT) with alternate function USART2_CK.
89 PB3 bidirectional 5 V tolerant I/O port PB3 (FT) whose main function is JTDO, with TRACESWO, TIM2_CH2 and SPI1_SCK alternate functions.
90 PB4 bidirectional 5 V tolerant I/O port PB4 (FT) whose main function is JNTRST, with TIM3_CH1 and SPI1_MISO alternate functions.
91 PB5 bidirectional Standard I/O port PB5 (not 5 V tolerant) with I2C1_SMBAI, TIM3_CH2 and SPI1_MOSI alternate functions.
92 PB6 bidirectional 5 V tolerant I/O port PB6 (FT) with I2C1_SCL, TIM4_CH1 and USART1_TX alternate functions.
93 PB7 bidirectional 5 V tolerant I/O port PB7 (FT) with I2C1_SDA, TIM4_CH2 and USART1_RX alternate functions.
94 BOOT0 input Boot mode selection input, specified from 0 to 5.5 V.
95 PB8 bidirectional 5 V tolerant I/O port PB8 (FT) with TIM4_CH3, I2C1_SCL and CANRX alternate functions.
96 PB9 bidirectional 5 V tolerant I/O port PB9 (FT) with TIM4_CH4, I2C1_SDA and CANTX alternate functions.
97 PE0 bidirectional 5 V tolerant I/O port PE0 (FT) with alternate function TIM4_ETR.
98 PE1 bidirectional 5 V tolerant I/O port PE1 (FT) with no alternate function listed in the pin table.
99 VSS_3 power_in Digital ground pin; all VDD and VSS pins must always be connected to the supply within the allowed range.
100 VDD_3 power_in Digital supply pin for I/O and the internal regulator, specified at 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer CKS
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating supply voltage (VDD, 2.0 V to 3.6 V) 2 3.6 V 2
Ambient operating temperature (product suffix 6) TA -40 85 ℃ Product name ends in suffix 6 2
Junction temperature -40 125 ℃ 2
CPU frequency 72 MHz 2
USB operating voltage (VDD USB) VDD 3 3.6 V 51
USB output low level (static) VOL 0.3 V RL = 1.5 kΩ to 3.6 V 51
USB output high level (static) VOH 2.8 3.6 V RL = 15 kΩ to VSS 51
USB differential common-mode range VCM 0.8 2.5 V Includes VDI range 51
USB single-ended receiver threshold VSE 1.3 2 V 51
USB rise time tr 4 20 ns CL ≤ 50 pF 51
USB fall time tf 4 20 ns CL ≤ 50 pF 51
USB rise/fall time matching (tr/tf) trfm 90 110 % 51
USB output signal crossover voltage VCRS 1.3 2 V 51
USB transceiver startup time tSTARTUP 1 μs 50
ADC supply voltage VDDA 2.4 3.6 V 52
ADC positive reference voltage VREF+ 2.4 V 52
ADC reference current IVREF 160 220 μA 52
ADC clock frequency fADC 0.6 14 MHz 52
ADC sampling rate fS 0.05 1 MHz 52
ADC external trigger frequency fTRIG 823 kHz fADC = 14 MHz 52
ADC external trigger frequency fTRIG 17 1/fADC 52
ADC external input impedance RAIN 50 kΩ 52
ADC sampling switch resistance RADC 1 kΩ 52
ADC sampling time tS 0.107 17.1 μs fADC = 14 MHz 52
ADC sampling time tS 1.5 239.5 1/fADC 52
ADC total conversion time (including sampling time) tCONV 1 18 μs fADC = 14 MHz 52
ADC total conversion time (including sampling time) tCONV 14 252 1/fADC 52
ADC power-up time tSTAB 0 0 1 μs 52

CAD (KiCad official)

  • Symbol: CKS32F103VBT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: cks32f103vbt6-etched.step / cks32f103vbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cks32f103vbt6.step / cks32f103vbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CKS datasheet (64 pp, sha256 221001e6207f4f99, retrieved 2026-10-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF