# CKS32F103RET6

**CKS** · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

CKS32F103RET6 from CKS, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup supply of 1.8 to 3.6 V for the RTC, external 32kHz oscillator and backup registers when VDD is off. |
| 2 | PC13-TAMPER-RTC | bidirectional | PC13 I/O (alternate TAMPER-RTC), powered through a switch that sinks only 3mA, so as output limited to 2MHz, 30pF load, no LED drive. |
| 3 | PC14-OSC32_IN | bidirectional | PC14 I/O (alternate OSC32_IN), powered through a 3mA-limited switch, output limited to 2MHz, 30pF. |
| 4 | PC15-OSC32_OUT | bidirectional | PC15 I/O (alternate OSC32_OUT), powered through a 3mA-limited switch, output limited to 2MHz, 30pF. |
| 5 | OSC_IN | input | 4-16MHz HSE oscillator input after reset; software can reconfigure as PD0 (no FSMC on this package). |
| 6 | OSC_OUT | output | 4-16MHz HSE oscillator output after reset; software can reconfigure as PD1 (output mode only 50MHz). |
| 7 | NRST | bidirectional | Device reset input/output with a non-disconnectable internal pull-up of 30-50kOhm, VIL max 0.8V. |
| 8 | PC0 | bidirectional | General-purpose I/O with alternate function ADC123_IN10. |
| 9 | PC1 | bidirectional | General-purpose I/O with alternate function ADC123_IN11. |
| 10 | PC2 | bidirectional | General-purpose I/O with alternate function ADC123_IN12. |
| 11 | PC3 | bidirectional | General-purpose I/O with alternate function ADC123_IN13. |
| 12 | VSSA | power_in | Analog ground for ADC, DAC, reset block, RC oscillators and PLL; must be connected to VSS. |
| 13 | VDDA | power_in | Analog supply of 2.0 to 3.6 V (2.4 V minimum when ADC/DAC used); must be connected to VDD; VREF+ is tied to it internally on this package. |
| 14 | PA0-WKUP | bidirectional | PA0 I/O with WKUP standby wake-up, USART2_CTS, ADC123_IN0, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR. |
| 15 | PA1 | bidirectional | General-purpose I/O with USART2_RTS, ADC123_IN1, TIM5_CH2, TIM2_CH2. |
| 16 | PA2 | bidirectional | General-purpose I/O with USART2_TX, TIM9_CH1, TIM5_CH3, ADC123_IN2, TIM2_CH3. |
| 17 | PA3 | bidirectional | General-purpose I/O with USART2_RX, TIM9_CH2, TIM5_CH4, ADC123_IN3, TIM2_CH4. |
| 18 | VSS_4 | power_in | Digital ground. |
| 19 | VDD_4 | power_in | Digital supply of 2.0 to 3.6 V for I/O and internal regulator. |
| 20 | PA4 | bidirectional | General-purpose I/O with SPI1_NSS, USART2_CK, DAC_OUT1, ADC12_IN4. |
| 21 | PA5 | bidirectional | General-purpose I/O with SPI1_SCK, DAC_OUT2, ADC12_IN5. |
| 22 | PA6 | bidirectional | General-purpose I/O with SPI1_MISO, TIM8_BKIN, ADC12_IN6, TIM13_CH1, TIM3_CH1, TIM1_BKIN. |
| 23 | PA7 | bidirectional | General-purpose I/O with SPI1_MOSI, TIM8_CH1N, ADC12_IN7, TIM14_CH1, TIM3_CH2, TIM1_CH1N. |
| 24 | PC4 | bidirectional | General-purpose I/O with alternate function ADC12_IN14. |
| 25 | PC5 | bidirectional | General-purpose I/O with alternate function ADC12_IN15. |
| 26 | PB0 | bidirectional | General-purpose I/O with ADC12_IN8, TIM3_CH3, TIM8_CH2N, TIM1_CH2N. |
| 27 | PB1 | bidirectional | General-purpose I/O with ADC12_IN9, TIM3_CH4, TIM8_CH3N, TIM1_CH3N. |
| 28 | PB2/BOOT1 | bidirectional | 5V-tolerant I/O that also serves as BOOT1 boot mode selection. |
| 29 | PB10 | bidirectional | 5V-tolerant I/O with I2C2_SCL, USART3_TX, TIM2_CH3. |
| 30 | PB11 | bidirectional | 5V-tolerant I/O with I2C2_SDA, USART3_RX, TIM2_CH4. |
| 31 | VSS_1 | power_in | Digital ground. |
| 32 | VDD_1 | power_in | Digital supply of 2.0 to 3.6 V for I/O and internal regulator. |
| 33 | PB12 | bidirectional | 5V-tolerant I/O with SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN. |
| 34 | PB13 | bidirectional | 5V-tolerant I/O with SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N. |
| 35 | PB14 | bidirectional | 5V-tolerant I/O with SPI2_MISO, USART3_RTS, TIM12_CH1, TIM1_CH2N. |
| 36 | PB15 | bidirectional | 5V-tolerant I/O with SPI2_MOSI, I2S2_SD, TIM12_CH2, TIM1_CH3N. |
| 37 | PC6 | bidirectional | 5V-tolerant I/O with I2S2_MCK, TIM8_CH1, USART6_TX, SDIO_D6, TIM3_CH1. |
| 38 | PC7 | bidirectional | 5V-tolerant I/O with I2S3_MCK, TIM8_CH2, USART6_RX, SDIO_D7, TIM3_CH2. |
| 39 | PC8 | bidirectional | 5V-tolerant I/O with TIM8_CH3, USART6_CK, SDIO_D0, TIM3_CH3. |
| 40 | PC9 | bidirectional | 5V-tolerant I/O with TIM8_CH4, SDIO_D1, TIM3_CH4. |
| 41 | PA8 | bidirectional | 5V-tolerant I/O with USART1_CK, TIM1_CH1, MCO. |
| 42 | PA9 | bidirectional | 5V-tolerant I/O with USART1_TX, TIM1_CH2. |
| 43 | PA10 | bidirectional | 5V-tolerant I/O with USART1_RX, TIM1_CH3. |
| 44 | PA11 | bidirectional | 5V-tolerant I/O with USART1_CTS, USBDM, CAN_RX, TIM1_CH4. |
| 45 | PA12 | bidirectional | 5V-tolerant I/O with USART1_RTS, USBDP, CAN_TX, TIM1_ETR. |
| 46 | PA13 | bidirectional | 5V-tolerant I/O, JTMS/SWDIO debug pin after reset. |
| 47 | VSS_2 | power_in | Digital ground. |
| 48 | VDD_2 | power_in | Digital supply of 2.0 to 3.6 V for I/O and internal regulator. |
| 49 | PA14 | bidirectional | 5V-tolerant I/O, JTCK/SWCLK debug pin after reset. |
| 50 | PA15 | bidirectional | 5V-tolerant I/O, JTDI after reset, with SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, SPI1_NSS. |
| 51 | PC10 | bidirectional | 5V-tolerant I/O with USART4_TX, SDIO_D2, USART3_TX. |
| 52 | PC11 | bidirectional | 5V-tolerant I/O with USART4_RX, SDIO_D3, USART3_RX. |
| 53 | PC12 | bidirectional | 5V-tolerant I/O with USART5_TX, SDIO_CK, USART3_CK. |
| 54 | PD2 | bidirectional | 5V-tolerant I/O with TIM3_ETR, USART5_RX, SDIO_CMD. |
| 55 | PB3 | bidirectional | 5V-tolerant I/O, JTDO after reset, with SPI3_SCK, I2S3_CK, TRACESWO, TIM2_CH2, SPI1_SCK. |
| 56 | PB4 | bidirectional | 5V-tolerant I/O, NJTRST after reset, with SPI3_MISO, TIM3_CH1, SPI1_MISO. |
| 57 | PB5 | bidirectional | I/O (not marked 5V-tolerant) with I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2, SPI1_MOSI. |
| 58 | PB6 | bidirectional | 5V-tolerant I/O with I2C1_SCL, TIM4_CH1, USART1_TX. |
| 59 | PB7 | bidirectional | 5V-tolerant I/O with I2C1_SDA, TIM4_CH2, USART1_RX (FSMC_NADV not available on this package). |
| 60 | BOOT0 | input | Boot mode selection input. |
| 61 | PB8 | bidirectional | 5V-tolerant I/O with TIM4_CH3, TIM10_CH1, SDIO_D4, I2C1_SCL, CAN_RX. |
| 62 | PB9 | bidirectional | 5V-tolerant I/O with TIM4_CH4, TIM11_CH1, SDIO_D5, I2C1_SDA, CAN_TX. |
| 63 | VSS_3 | power_in | Digital ground. |
| 64 | VDD_3 | power_in | Digital supply of 2.0 to 3.6 V for I/O and internal regulator. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | CKS |
| Package | LQFP-64(10x10) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply and I/O voltage (feature list) | VDD | 2 |  | 3.6 | V | 2.0~3.6V supply and I/O pins | 1 |
| USB operating voltage | VDD | 3 |  | 3.6 | V | USB operation | 83 |
| USB differential input sensitivity | VDI | 0.2 |  |  | V | I(USBDP,USBDM) | 83 |
| USB differential common mode range | VCM | 0.8 |  | 2.5 | V | Includes VDI range | 83 |
| USB single-ended receiver threshold | VSE | 1.3 |  | 2 | V |  | 83 |
| USB static output low level | VOL |  |  | 0.3 | V | RL of 1.5kΩ to 3.6V | 83 |
| USB static output high level | VOH | 2.8 |  | 3.6 | V | RL of 15kΩ to VSS | 83 |
| USB transceiver startup time | tSTARTUP |  |  | 1 | μs |  | 83 |
| USB rise time | tr | 4 |  | 20 | ns | CL ≤ 50pF | 84 |
| USB fall time | tf | 4 |  | 20 | ns | CL ≤ 50pF | 84 |
| USB rise/fall time matching | trfm | 90 |  | 110 | % | tr / tf | 84 |
| USB output signal crossover voltage | VCRS | 1.3 |  | 2 | V |  | 84 |
| ADC supply voltage | VDDA | 2.4 |  | 3.6 | V |  | 84 |
| ADC positive reference voltage | VREF+ | 2.4 |  |  | V | Upper limit printed as VDDA | 84 |
| Current on VREF input pin | IVREF |  | 160 | 220 | μA |  | 84 |
| ADC clock frequency | fADC | 0.6 |  | 14 | MHz |  | 84 |
| ADC sampling rate | fS | 0.05 |  | 1 | MHz |  | 84 |
| External trigger frequency | fTRIG |  |  | 823 | kHz | fADC=14MHz | 84 |
| Conversion voltage range | VAIN | 0 |  |  | V | 0 (VSSA or VREF- connected to ground) to VREF+ | 84 |
| Sampling switch resistance | RADC |  |  | 1 | kΩ |  | 84 |
| Internal sample and hold capacitor | CADC |  | 12 |  | pF |  | 84 |
| Calibration time | tCAL |  | 5.9 |  | μs | fADC=14MHz | 84 |
| Sampling time | tS | 0.107 |  | 17.1 | μs | fADC=14MHz | 85 |
| Sampling time (cycles) | tS | 1.5 |  | 239.5 | 1/fADC |  | 85 |
| Power-up time | tSTAB | 0 | 0 | 1 | μs |  | 85 |
| Total conversion time (including sampling time) | tCONV | 1 |  | 18 | μs | fADC=14MHz | 85 |
| Total conversion time (cycles) | tCONV | 14 |  | 252 | 1/fADC | sampling tS + successive approximation 12.5 | 85 |
| ADC total unadjusted error | ET |  | 1.3 | 2 | LSB | fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3~3.6V, TA= 25 °C, after ADC calibration, VREF+=VDDA | 85 |
| ADC offset error | EO |  | 1 | 1.5 | LSB | fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3~3.6V, TA= 25 °C, after ADC calibration, VREF+=VDDA | 85 |
| ADC gain error | EG |  | 0.5 | 1.5 | LSB | fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3~3.6V, TA= 25 °C, after ADC calibration, VREF+=VDDA | 85 |
| ADC differential linearity error | ED |  | 0.7 | 1 | LSB | fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3~3.6V, TA= 25 °C, after ADC calibration, VREF+=VDDA | 85 |
| ADC integral linearity error | EL |  | 0.8 | 1.5 | LSB | fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3~3.6V, TA= 25 °C, after ADC calibration, VREF+=VDDA | 85 |

## CAD (KiCad official)

- Symbol: `CKS32F103RET6`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `cks32f103ret6-etched.step` / `cks32f103ret6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cks32f103ret6.step` / `cks32f103ret6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [CKS datasheet](docs/cks32f103ret6-datasheet.pdf) (98 pp, sha256 `3b7626fd9350b985`, retrieved 2026-10-23, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cks32f103ret6-datasheet.pdf)