component
CKS32F103RBT6
Public Made by Adomby adom
CKS Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCKS32F103RBT6
CKS · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
CKS32F103RBT6 from CKS, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup battery input, 1.8-3.6V. Powers RTC, LSE oscillator and backup registers when VDD is off. |
| 2 | PC13-TAMPER-RTC | bidirectional | GPIO Port C bit 13; alt-function TAMPER input and RTC output. Backup-domain supplied via power switch, limited to 3mA / 2MHz / 30pF; not suitable for current-sourcing. |
| 3 | PC14-OSC32_IN | bidirectional | GPIO Port C bit 14 / 32.768 kHz LSE crystal input. Backup-domain supplied; drive limited to 3mA / 2MHz / 30pF. |
| 4 | PC15-OSC32_OUT | bidirectional | GPIO Port C bit 15 / 32.768 kHz LSE crystal output. Backup-domain supplied; drive limited to 3mA / 2MHz / 30pF. |
| 5 | OSC_IN/PD0 | input | HSE crystal input (default after reset). Software-remappable to GPIO PD0. |
| 6 | OSC_OUT/PD1 | output | HSE crystal output (default after reset). Software-remappable to GPIO PD1. |
| 7 | NRST | bidirectional | Bidirectional active-low reset. Internal weak pull-up; drive low to reset MCU. |
| 8 | PC0 | bidirectional | GPIO Port C bit 0; alt-function ADC12_IN10. |
| 9 | PC1 | bidirectional | GPIO Port C bit 1; alt-function ADC12_IN11. |
| 10 | PC2 | bidirectional | GPIO Port C bit 2; alt-function ADC12_IN12. |
| 11 | PC3 | bidirectional | GPIO Port C bit 3; alt-function ADC12_IN13. |
| 12 | VSSA | power_in | Analog ground reference for ADC and VREF. Also the internal VREF- on LQFP64. |
| 13 | VDDA | power_in | Analog supply, 2.0-3.6V. Also the internal VREF+ on LQFP64. |
| 14 | PA0-WKUP | bidirectional | GPIO Port A bit 0; alt WKUP wake-from-Standby / USART2_CTS / ADC12_IN0 / TIM2_CH1_ETR. |
| 15 | PA1 | bidirectional | GPIO Port A bit 1; alt USART2_RTS / ADC12_IN1 / TIM2_CH2. |
| 16 | PA2 | bidirectional | GPIO Port A bit 2; alt USART2_TX / ADC12_IN2 / TIM2_CH3. |
| 17 | PA3 | bidirectional | GPIO Port A bit 3; alt USART2_RX / ADC12_IN3 / TIM2_CH4. |
| 18 | VSS_4 | power_in | Digital ground. |
| 19 | VDD_4 | power_in | Digital supply, 2.0-3.6V. |
| 20 | PA4 | bidirectional | GPIO Port A bit 4; alt SPI1_NSS / USART2_CK / ADC12_IN4. |
| 21 | PA5 | bidirectional | GPIO Port A bit 5; alt SPI1_SCK / ADC12_IN5. |
| 22 | PA6 | bidirectional | GPIO Port A bit 6; alt SPI1_MISO / ADC12_IN6 / TIM3_CH1 / TIM1_BKIN. |
| 23 | PA7 | bidirectional | GPIO Port A bit 7; alt SPI1_MOSI / ADC12_IN7 / TIM3_CH2 / TIM1_CH1N. |
| 24 | PC4 | bidirectional | GPIO Port C bit 4; alt ADC12_IN14. |
| 25 | PC5 | bidirectional | GPIO Port C bit 5; alt ADC12_IN15. |
| 26 | PB0 | bidirectional | GPIO Port B bit 0; alt ADC12_IN8 / TIM3_CH3 / TIM1_CH2N. |
| 27 | PB1 | bidirectional | GPIO Port B bit 1; alt ADC12_IN9 / TIM3_CH4 / TIM1_CH3N. |
| 28 | PB2/BOOT1 | bidirectional | GPIO Port B bit 2; also BOOT1 boot-mode select strap sampled at reset. 5V-tolerant (FT). |
| 29 | PB10 | bidirectional | GPIO Port B bit 10; alt I2C2_SCL / USART3_TX / TIM2_CH3. 5V-tolerant. |
| 30 | PB11 | bidirectional | GPIO Port B bit 11; alt I2C2_SDA / USART3_RX / TIM2_CH4. 5V-tolerant. |
| 31 | VSS_1 | power_in | Digital ground. |
| 32 | VDD_1 | power_in | Digital supply, 2.0-3.6V. |
| 33 | PB12 | bidirectional | GPIO Port B bit 12; alt SPI2_NSS / I2C2_SMBAI / USART3_CK / TIM1_BKIN. 5V-tolerant. |
| 34 | PB13 | bidirectional | GPIO Port B bit 13; alt SPI2_SCK / USART3_CTS / TIM1_CH1N. 5V-tolerant. |
| 35 | PB14 | bidirectional | GPIO Port B bit 14; alt SPI2_MISO / USART3_RTS / TIM1_CH2N. 5V-tolerant. |
| 36 | PB15 | bidirectional | GPIO Port B bit 15; alt SPI2_MOSI / TIM1_CH3N. 5V-tolerant. |
| 37 | PC6 | bidirectional | GPIO Port C bit 6; alt TIM3_CH1. 5V-tolerant. |
| 38 | PC7 | bidirectional | GPIO Port C bit 7; alt TIM3_CH2. 5V-tolerant. |
| 39 | PC8 | bidirectional | GPIO Port C bit 8; alt TIM3_CH3. 5V-tolerant. |
| 40 | PC9 | bidirectional | GPIO Port C bit 9; alt TIM3_CH4. 5V-tolerant. |
| 41 | PA8 | bidirectional | GPIO Port A bit 8; alt USART1_CK / TIM1_CH1 / MCO. 5V-tolerant. |
| 42 | PA9 | bidirectional | GPIO Port A bit 9; alt USART1_TX / TIM1_CH2. 5V-tolerant. |
| 43 | PA10 | bidirectional | GPIO Port A bit 10; alt USART1_RX / TIM1_CH3. 5V-tolerant. |
| 44 | PA11 | bidirectional | GPIO Port A bit 11; alt USART1_CTS / USBDM / CANRX / TIM1_CH4. 5V-tolerant. |
| 45 | PA12 | bidirectional | GPIO Port A bit 12; alt USART1_RTS / USBDP / CANTX / TIM1_ETR. 5V-tolerant. |
| 46 | PA13 | bidirectional | GPIO Port A bit 13; default JTMS/SWDIO after reset. 5V-tolerant. |
| 47 | VSS_2 | power_in | Digital ground. |
| 48 | VDD_2 | power_in | Digital supply, 2.0-3.6V. |
| 49 | PA14 | bidirectional | GPIO Port A bit 14; default JTCK/SWCLK after reset. 5V-tolerant. |
| 50 | PA15 | bidirectional | GPIO Port A bit 15; default JTDI after reset. Alt TIM2_CH1_ETR / PA15 / SPI1_NSS. 5V-tolerant. |
| 51 | PC10 | bidirectional | GPIO Port C bit 10; alt USART3_TX. 5V-tolerant. |
| 52 | PC11 | bidirectional | GPIO Port C bit 11; alt USART3_RX. 5V-tolerant. |
| 53 | PC12 | bidirectional | GPIO Port C bit 12; alt USART3_CK. 5V-tolerant. |
| 54 | PD2 | bidirectional | GPIO Port D bit 2; alt TIM3_ETR. 5V-tolerant. |
| 55 | PB3 | bidirectional | GPIO Port B bit 3; default JTDO after reset. Alt PB3/TRACESWO/TIM2_CH2/SPI1_SCK. 5V-tolerant. |
| 56 | PB4 | bidirectional | GPIO Port B bit 4; default JNTRST after reset. Alt PB4/TIM3_CH1/SPI1_MISO. 5V-tolerant. |
| 57 | PB5 | bidirectional | GPIO Port B bit 5; alt I2C1_SMBAI / TIM3_CH2 / SPI1_MOSI. Not 5V-tolerant. |
| 58 | PB6 | bidirectional | GPIO Port B bit 6; alt I2C1_SCL / TIM4_CH1 / USART1_TX. 5V-tolerant. |
| 59 | PB7 | bidirectional | GPIO Port B bit 7; alt I2C1_SDA / TIM4_CH2 / USART1_RX. 5V-tolerant. |
| 60 | BOOT0 | input | Boot-mode select strap sampled at reset. Combined with BOOT1 (PB2) selects boot from main Flash, system memory (bootloader), or SRAM. |
| 61 | PB8 | bidirectional | GPIO Port B bit 8; alt I2C1_SCL / TIM4_CH3 / CANRX. 5V-tolerant. |
| 62 | PB9 | bidirectional | GPIO Port B bit 9; alt I2C1_SDA / TIM4_CH4 / CANTX. 5V-tolerant. |
| 63 | VSS_3 | power_in | Digital ground. |
| 64 | VDD_3 | power_in | Digital supply, 2.0-3.6V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CKS |
| Package | LQFP-64(10x10) |
| Category | MCU |
| Pins | 64 |
Ordering variants
Same part, different packaging or reel option.
CKS32F103RBT6R8T6CKS32F103RBT6CKS32F103RBT6RBT7CKS32F103RBT6C8T6CKS32F103RBT6CBT6CKS32F103RBT6VBT6
CAD (KiCad official)
- Symbol:
CKS32F103RBT6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
cks32f103rbt6-etched.step/cks32f103rbt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cks32f103rbt6.step/cks32f103rbt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CKS datasheet (64 pp, sha256
221001e6207f4f99, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).