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CKS32F051R8T6

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CKS Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CKS32F051R8T6

CKS · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

CKS32F051R8T6 from CKS, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup power supply for the RTC, external 32 kHz oscillator and backup registers when VDD is off, specified at 1.65 to 3.6 V.
2 PC13 bidirectional Backup-domain 3.3 V standard I/O (TC) with RTC tamper/timestamp/output and WKUP2 alternate functions; sink current is limited to 3 mA through the power switch.
3 PC14/OSC32_IN bidirectional Backup-domain 3.3 V standard I/O (TC) whose alternate function is the OSC32_IN input of the 32.768 kHz oscillator, with the same power-switch output limits as PC13.
4 PC15/OSC32_OUT bidirectional Backup-domain 3.3 V standard I/O (TC) whose alternate function is the OSC32_OUT output of the 32.768 kHz oscillator, with the same power-switch output limits as PC13.
5 PF0/OSC_IN bidirectional 5 V tolerant I/O (FT) whose alternate function is OSC_IN, the 4-32 MHz high-speed external oscillator input.
6 PF1/OSC_OUT bidirectional 5 V tolerant I/O (FT) whose alternate function is OSC_OUT, the high-speed external oscillator output.
7 NRST bidirectional Active-low device reset input and internal reset output with a weak pull-up that cannot be disabled (RST structure).
8 PC0 bidirectional 3.3 V tolerant I/O (TTa) connected directly to ADC input ADC_IN10, with EVENTOUT alternate function.
9 PC1 bidirectional 3.3 V tolerant I/O (TTa) connected directly to ADC input ADC_IN11, with EVENTOUT alternate function.
10 PC2 bidirectional 3.3 V tolerant I/O (TTa) connected directly to ADC input ADC_IN12, with EVENTOUT alternate function.
11 PC3 bidirectional 3.3 V tolerant I/O (TTa) connected directly to ADC input ADC_IN13, with EVENTOUT alternate function.
12 VSSA power_in Analog ground for the ADC, DAC, comparators, reset block, RC oscillators and PLL; all voltages are referenced to VSS.
13 VDDA power_in Analog supply 2.0 to 3.6 V for the ADC, reset block, RC oscillators and PLL (2.4 V minimum when ADC/DAC are used); must be equal to or higher than VDD and powered first.
14 PA0 bidirectional 3.3 V tolerant I/O (TTa) with ADC_IN0, COMP1_INM6, RTC_TAMP2 and WKUP1 functions; alternate functions include USART2_CTS, TIM2_CH1_ETR, COMP1_OUT and TSC_G1_IO1.
15 PA1 bidirectional 3.3 V tolerant I/O (TTa) with ADC_IN1 and COMP1_INP inputs; alternate functions include USART2_RTS, TIM2_CH2, TSC_G1_IO2 and EVENTOUT.
16 PA2 bidirectional 3.3 V tolerant I/O (TTa) with ADC_IN2 and COMP2_INM6 inputs; alternate functions include USART2_TX, TIM2_CH3, TIM15_CH1, COMP2_OUT and TSC_G1_IO3.
17 PA3 bidirectional 3.3 V tolerant I/O (TTa) with ADC_IN3 and COMP2_INP inputs; alternate functions include USART2_RX, TIM2_CH4, TIM15_CH2 and TSC_G1_IO4.
18 PF4 bidirectional 5 V tolerant I/O (FT) with EVENTOUT alternate function.
19 PF5 bidirectional 5 V tolerant I/O (FT) with EVENTOUT alternate function.
20 PA4 bidirectional 3.3 V tolerant I/O (TTa) with ADC_IN4, COMP1_INM4, COMP2_INM4 and DAC1_OUT analog functions; alternate functions include SPI1_NSS/I2S1_WS, USART2_CK, TIM14_CH1 and TSC_G2_IO1.
21 PA5 bidirectional 3.3 V tolerant I/O (TTa) with ADC_IN5, COMP1_INM5 and COMP2_INM5 inputs; alternate functions include SPI1_SCK/I2S1_CK, CEC, TIM2_CH_ETR and TSC_G2_IO2.
22 PA6 bidirectional 3.3 V tolerant I/O (TTa) with ADC_IN6 input; alternate functions include SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3 and EVENTOUT.
23 PA7 bidirectional 3.3 V tolerant I/O (TTa) with ADC_IN7 input; alternate functions include SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, TSC_G2_IO4 and EVENTOUT.
24 PC4 bidirectional 3.3 V tolerant I/O (TTa) with ADC_IN14 input and EVENTOUT alternate function.
25 PC5 bidirectional 3.3 V tolerant I/O (TTa) with ADC_IN15 input and TSC_G3_IO1 touch-sensing alternate function.
26 PB0 bidirectional 3.3 V tolerant I/O (TTa) with ADC_IN8 input; alternate functions include TIM3_CH3, TIM1_CH2N, TSC_G3_IO2 and EVENTOUT.
27 PB1 bidirectional 3.3 V tolerant I/O (TTa) with ADC_IN9 input; alternate functions include TIM3_CH4, TIM14_CH1, TIM1_CH3N and TSC_G3_IO3.
28 PB2 bidirectional 5 V tolerant I/O (FT) with TSC_G3_IO4 touch-sensing alternate function.
29 PB10 bidirectional 5 V tolerant I/O (FT) with alternate functions I2C2_SCL, CEC, TIM2_CH3 and TSC_SYNC.
30 PB11 bidirectional 5 V tolerant I/O (FT) with alternate functions I2C2_SDA, TIM2_CH4, TSC_G6_IO1 and EVENTOUT.
31 VSS power_in Digital ground pin for the I/O and core; all voltages are referenced to VSS.
32 VDD power_in Digital supply 2.0 to 3.6 V for the I/O and internal regulator, supplied externally on the VDD pin.
33 PB12 bidirectional 5 V tolerant I/O (FT) with alternate functions SPI2_NSS, TIM1_BKIN, TSC_G6_IO2 and EVENTOUT.
34 PB13 bidirectional 5 V tolerant I/O (FT) with alternate functions SPI2_SCK, TIM1_CH1N and TSC_G6_IO3.
35 PB14 bidirectional 5 V tolerant I/O (FT) with alternate functions SPI2_MISO, TIM15_CH1, TIM1_CH2N and TSC_G6_IO4.
36 PB15 bidirectional 5 V tolerant I/O (FT) with alternate functions SPI2_MOSI, TIM15_CH2, TIM1_CH3N, TIM15_CH1N and RTC_REFIN.
37 PC6 bidirectional 5 V tolerant I/O (FT) with TIM3_CH1 alternate function.
38 PC7 bidirectional 5 V tolerant I/O (FT) with TIM3_CH2 alternate function.
39 PC8 bidirectional 5 V tolerant I/O (FT) with TIM3_CH3 alternate function.
40 PC9 bidirectional 5 V tolerant I/O (FT) with TIM3_CH4 alternate function.
41 PA8 bidirectional 5 V tolerant I/O (FT) with alternate functions USART1_CK, TIM1_CH1, EVENTOUT and MCO.
42 PA9 bidirectional 5 V tolerant I/O (FT) with alternate functions USART1_TX, TIM1_CH2, TIM15_BKIN and TSC_G4_IO1.
43 PA10 bidirectional 5 V tolerant I/O (FT) with alternate functions USART1_RX, TIM1_CH3, TIM17_BKIN and TSC_G4_IO2.
44 PA11 bidirectional 5 V tolerant I/O (FT) with alternate functions USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3 and EVENTOUT.
45 PA12 bidirectional 5 V tolerant I/O (FT) with alternate functions USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4 and EVENTOUT.
46 PA13(SWDAT) bidirectional 5 V tolerant I/O (FT) that defaults to SWDAT after reset with internal pull-up enabled; alternate function IR_OUT.
47 PF6 bidirectional 5 V tolerant I/O (FT) with alternate function I2C2_SCL.
48 PF7 bidirectional 5 V tolerant I/O (FT) with alternate function I2C2_SDA.
49 PA14(SWCLK) bidirectional 5 V tolerant I/O (FT) that defaults to SWCLK after reset with internal pull-down enabled; alternate function USART2_TX.
50 PA15 bidirectional 5 V tolerant I/O (FT) with alternate functions SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH_ETR and EVENTOUT.
51 PC10 bidirectional 5 V tolerant GPIO (FT); no alternate function is listed for this pin in the datasheet pin table.
52 PC11 bidirectional 5 V tolerant GPIO (FT); no alternate function is listed for this pin in the datasheet pin table.
53 PC12 bidirectional 5 V tolerant GPIO (FT); no alternate function is listed for this pin in the datasheet pin table.
54 PD2 bidirectional 5 V tolerant I/O (FT) with TIM3_ETR alternate function.
55 PB3 bidirectional 5 V tolerant I/O (FT) with alternate functions SPI1_SCK/I2S1_CK, TIM2_CH2, TSC_G5_IO1 and EVENTOUT.
56 PB4 bidirectional 5 V tolerant I/O (FT) with alternate functions SPI1_MISO/I2S1_MCK, TIM3_CH1, TSC_G5_IO2 and EVENTOUT.
57 PB5 bidirectional 5 V tolerant I/O (FT) with alternate functions SPI1_MOSI/I2S1_SD, I2C1_SMBA, TIM16_BKIN and TIM3_CH2.
58 PB6 bidirectional 5 V tolerant I/O with FM+ capability (FTf) with alternate functions I2C1_SCL, USART1_TX, TIM16_CH1N and TSC_G5_IO3.
59 PB7 bidirectional 5 V tolerant I/O with FM+ capability (FTf) with alternate functions I2C1_SDA, USART1_RX, TIM17_CH1N and TSC_G5_IO4.
60 BOOT0 input Dedicated boot memory selection pin, input only; it must be externally pulled high or low and must not be left floating (0 to 5.5 V per Table 19).
61 PB8 bidirectional 5 V tolerant I/O with FM+ capability (FTf) with alternate functions I2C1_SCL, CEC, TIM16_CH1 and TSC_SYNC.
62 PB9 bidirectional 5 V tolerant I/O with FM+ capability (FTf) with alternate functions I2C1_SDA, IR_OUT, TIM17_CH1 and EVENTOUT.
63 VSS power_in Digital ground pin; all voltages are referenced to VSS.
64 VDD power_in Digital supply 2.0 to 3.6 V for the I/O and internal regulator.

Key specifications

Parameter Value
Manufacturer CKS
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: CKS32F051R8T6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: cks32f051r8t6-etched.step / cks32f051r8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cks32f051r8t6.step / cks32f051r8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CKS datasheet (91 pp, sha256 e733607a3ed17f59, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF