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CKS32F031C6T6

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CKS Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CKS32F031C6T6

CKS · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

CKS32F031C6T6 from CKS, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup supply of 1.71 to 3.6 V that powers the RTC, the external 32 kHz oscillator and the backup registers when VDD is absent.
2 PC13 bidirectional TC (standard 3.3 V) I/O whose supply passes through a power switch that sinks at most 3 mA, so GPIO output is limited to 2 MHz at 30 pF and it cannot source current such as LED drive; also RTC_TAMP1, RTC_TS, RTC_OUT and WKUP2.
3 PC14-OSC32_IN bidirectional TC I/O (PC14) that doubles as the 32.768 kHz oscillator input OSC32_IN, with the same power-switch and output limits as PC13.
4 PC15-OSC32_OUT bidirectional TC I/O (PC15) that doubles as the 32.768 kHz oscillator output OSC32_OUT, with the same power-switch and output limits as PC13.
5 PF0-OSC_IN bidirectional 5 V tolerant FT I/O (PF0) that doubles as the HSE oscillator input OSC_IN for a 4 to 32 MHz crystal or an external clock of 8 to 32 MHz in bypass mode.
6 PF1-OSC_OUT bidirectional 5 V tolerant FT I/O (PF1) that doubles as the HSE oscillator output OSC_OUT.
7 NRST bidirectional Active-low device reset input and internal reset output with an internal pull-up of 25 to 55 kΩ (40 kΩ typical), with VIL(NRST) max of 0.3VDD+0.07 V.
8 VSSA power_in Analog ground; per footnote 3 the chip's VSSA pad is connected internally to the VSS pin.
9 VDDA power_in Analog supply for the ADC, reset block, RC oscillators and PLL, which must be greater than or equal to VDD and 2.4 to 3.6 V when the ADC is used.
10 PA0 bidirectional TTa 3.3 V tolerant I/O connected directly to the ADC; alternate functions USART1_CTS and TIM2_CH1_ETR; additional functions ADC_IN0, RTC_TAMP2 and WKUP1.
11 PA1 bidirectional TTa 3.3 V tolerant I/O connected directly to the ADC; alternate functions USART1_RTS, TIM2_CH2 and EVENTOUT; additional function ADC_IN1.
12 PA2 bidirectional TTa 3.3 V tolerant I/O connected directly to the ADC; alternate functions USART1_TX and TIM2_CH3; additional function ADC_IN2.
13 PA3 bidirectional TTa 3.3 V tolerant I/O connected directly to the ADC; alternate functions USART1_RX and TIM2_CH4; additional function ADC_IN3.
14 PA4 bidirectional TTa 3.3 V tolerant I/O connected directly to the ADC; alternate functions SPI1_NSS, I2S1_WS, USART1_CK and TIM14_CH1; additional function ADC_IN4.
15 PA5 bidirectional TTa 3.3 V tolerant I/O connected directly to the ADC; alternate functions SPI1_SCK, I2S1_CK and TIM2_CH1_ETR; additional function ADC_IN5.
16 PA6 bidirectional TTa 3.3 V tolerant I/O connected directly to the ADC; alternate functions SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1 and EVENTOUT; additional function ADC_IN6.
17 PA7 bidirectional TTa 3.3 V tolerant I/O connected directly to the ADC; alternate functions SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1 and EVENTOUT; additional function ADC_IN7.
18 PB0 bidirectional TTa 3.3 V tolerant I/O connected directly to the ADC; alternate functions TIM3_CH3, TIM1_CH2N and EVENTOUT; additional function ADC_IN8.
19 PB1 bidirectional TTa 3.3 V tolerant I/O connected directly to the ADC; alternate functions TIM3_CH4, TIM14_CH1 and TIM1_CH3N; additional function ADC_IN9.
20 PB2 bidirectional 5 V tolerant FT I/O with no alternate function listed in the pin definition table.
21 PB10 bidirectional 5 V tolerant FTf I/O with FM+ capability; alternate functions I2C1_SCL and TIM2_CH3.
22 PB11 bidirectional 5 V tolerant FTf I/O with FM+ capability; alternate functions TIM2_CH4, EVENTOUT and I2C1_SDA.
23 VSS power_in Digital ground.
24 VDD power_in Digital and I/O supply, 2.0 to 3.6 V per section 3.5.1 (Table 17 lists a 2.4 V minimum).
25 PB12 bidirectional 5 V tolerant FT I/O; alternate functions SPI1_NSS, TIM1_BKIN and EVENTOUT.
26 PB13 bidirectional 5 V tolerant FT I/O; alternate functions SPI1_SCK and TIM1_CH1N.
27 PB14 bidirectional 5 V tolerant FT I/O; alternate functions SPI1_MISO and TIM1_CH2N.
28 PB15 bidirectional 5 V tolerant FT I/O; alternate functions SPI1_MOSI, TIM1_CH3N and RTC_REFIN.
29 PA8 bidirectional 5 V tolerant FT I/O; alternate functions USART1_CK, TIM1_CH1, EVENTOUT and MCO.
30 PA9 bidirectional 5 V tolerant FTf I/O with FM+ capability; alternate functions USART1_TX, TIM1_CH2 and I2C1_SCL.
31 PA10 bidirectional 5 V tolerant FTf I/O with FM+ capability; alternate functions USART1_RX, TIM1_CH3, TIM17_BKIN and I2C1_SDA.
32 PA11 bidirectional 5 V tolerant FT I/O; alternate functions USART1_CTS, TIM1_CH4 and EVENTOUT.
33 PA12 bidirectional 5 V tolerant FT I/O; alternate functions USART1_RTS, TIM1_ETR and EVENTOUT.
34 PA13 bidirectional 5 V tolerant FT I/O that after reset is SWDIO with internal pull-up enabled; alternate function IR_OUT.
35 PF6 bidirectional 5 V tolerant FTf I/O with FM+ capability; alternate function I2C1_SCL.
36 PF7 bidirectional 5 V tolerant FTf I/O with FM+ capability; alternate function I2C1_SDA.
37 PA14 bidirectional 5 V tolerant FT I/O that after reset is SWCLK with internal pull-down enabled; alternate function USART1_TX.
38 PA15 bidirectional 5 V tolerant FT I/O; alternate functions SPI1_NSS, I2S1_WS, USART1_RX, TIM2_CH_ETR and EVENTOUT.
39 PB3 bidirectional 5 V tolerant FT I/O; alternate functions SPI1_SCK, I2S1_CK, EVENTOUT and TIM2_CH2.
40 PB4 bidirectional 5 V tolerant FT I/O; alternate functions SPI1_MISO, I2S1_MCK, TIM3_CH1 and EVENTOUT.
41 PB5 bidirectional 5 V tolerant FT I/O; alternate functions SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN and TIM3_CH2.
42 PB6 bidirectional 5 V tolerant FTf I/O with FM+ capability; alternate functions I2C1_SCL, USART1_TX and TIM16_CH1N.
43 PB7 bidirectional 5 V tolerant FTf I/O with FM+ capability; alternate functions I2C1_SDA, USART1_RX and TIM17_CH1N.
44 BOOT0 input Boot memory selection input, input-only, which must be pulled high or low externally and must not be left floating; operating range 0 to 5.5 V.
45 PB8 bidirectional 5 V tolerant FTf I/O with FM+ capability; alternate functions I2C1_SCL and TIM16_CH1.
46 PB9 bidirectional 5 V tolerant FTf I/O with FM+ capability; alternate functions I2C1_SDA, IR_OUT, TIM17_CH1 and EVENTOUT.
47 VSS power_in Digital ground.
48 VDD power_in Digital and I/O supply, 2.0 to 3.6 V per section 3.5.1.

Key specifications

Parameter Value
Manufacturer CKS
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

CAD (KiCad official)

  • Symbol: CKS32F031C6T6
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: cks32f031c6t6-etched.step / cks32f031c6t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cks32f031c6t6.step / cks32f031c6t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CKS datasheet (92 pp, sha256 2baab798b6caacdc, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF