component
CJQ13P04
Public Made by Adomby adom
Changjing MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 21d ago |
| viewers | 21d ago |
| cjq13p04-etched.glb | 21d ago |
| cjq13p04-etched.step | 21d ago |
| cjq13p04-hero.glb | 21d ago |
| cjq13p04-hero.overlay.json | 21d ago |
| cjq13p04.glb | 21d ago |
| cjq13p04.kicad_mod | 21d ago |
| cjq13p04.kicad_sym | 21d ago |
| cjq13p04.lbr | 21d ago |
| cjq13p04.step | 21d ago |
| package.json | 21d ago |
| page.json | 16d ago |
| README.md | 16d ago |
CJQ13P04
Changjing · MOSFETs · SOP-8
CJQ13P04 from Changjing, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied internally with pins 2 and 3 (equivalent circuit). |
| 2 | S | passive | Source of the P-channel MOSFET, tied internally with pins 1 and 3 (equivalent circuit). |
| 3 | S | passive | Source of the P-channel MOSFET, tied internally with pins 1 and 2 (equivalent circuit). |
| 4 | G | input | Gate of the P-channel MOSFET with threshold VGS(th) of -1.0 V min to -2.5 V max at ID=-250µA and leakage tested at VGS=±20V. |
| 5 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 6, 7 and 8, with V(BR)DSS of -40 V. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 7 and 8, with V(BR)DSS of -40 V. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 6 and 8, with V(BR)DSS of -40 V. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 6 and 7, with V(BR)DSS of -40 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Changjing |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source breakdown voltage | V(BR)DSS | -40 | V | VGS=0V, ID=-250µA | 2 | ||
| Zero gate voltage drain current | IDSS | -1 | µA | VDS=-40V, VGS=0V | 2 | ||
| Gate-body leakage current | IGSS | -100 | 100 | nA | VDS=0V, VGS=±20V | 2 | |
| Gate-threshold voltage | VGS(th) | -1 | -1.5 | -2.5 | V | VDS=VGS, ID=-250µA | 2 |
| Static drain-source on-state resistance | RDS(on) | 11 | mΩ | VGS=-10V, ID=-10A | 2 | ||
| Static drain-source on-state resistance | RDS(on) | 14.5 | mΩ | VGS=-4.5V, ID=-8A | 2 | ||
| Drain-source diode forward voltage | VSD | -1.2 | V | VGS=0V, IS=-1A | 2 | ||
| Continuous drain-source diode forward current | IS | -13 | A | 2 | |||
| Pulsed drain-source diode forward current | ISM | -52 | A | 2 | |||
| Single pulsed avalanche energy | EAS | 200 | mJ | VDD=-20V, VGS=-10V, L=0.5mH, Rg=25Ω, starting TJ=25°C | 1 | ||
| Thermal resistance, junction to ambient | RθJA | 89 | ℃/W | Device mounted on 1 in² FR-4 board with 2oz copper, still air, Ta=25℃ | 1 |
CAD (KiCad official)
- Symbol:
CJQ13P04 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
cjq13p04-etched.step/cjq13p04-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cjq13p04.step/cjq13p04.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Changjing datasheet (5 pp, sha256
71deb09e143b3229, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).