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CJC8990

Public Made by Adom

by adom

ESHINE Signal Switches / Encoders & Decoders / Multiplexers, QFN4x4-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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CJC8990

ESHINE · Signal Switches / Encoders & Decoders / Multiplexers · QFN4x4-20

CJC8990 from ESHINE, in a QFN4x4-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DCVDD power_in Digital core supply and digital I/O supply. Operating range 1.8 V to 3.3 V (core can be run down to 1.5 V). Absolute max 3.6 V; decouple locally.
2 DGND power_in Digital ground, return path for both DCVDD and DBVDD. Must be within 0.3 V of AGND.
3 BCLK bidirectional Audio interface bit clock. Direction depends on master/slave mode of the digital audio interface (output in master mode, input in slave mode).
4 DACDAT input DAC digital audio data input to the stereo DAC over the audio interface.
5 LRC bidirectional Audio interface left/right (word) clock. Direction depends on master/slave mode (output in master mode, input in slave mode).
6 ADCDAT output ADC digital audio data output from the stereo ADC over the audio interface.
7 HPCOM output LOUT/ROUT common-mode output used as the ground reference for capless (BTL-style) headphone connection. Nominally biased around mid-rail (VMID).
8 ROUT output Right analogue output for headphone or line-out use, driven by the on-chip headphone driver (16 Ω capable).
9 LOUT output Left analogue output for headphone or line-out use, driven by the on-chip headphone driver (16 Ω capable).
10 HPGND power_in Ground return for the analogue output (headphone) drivers LOUT/ROUT. Keep low-impedance to speaker/headphone jack ground.
11 HPVDD power_in Supply for the analogue output drivers (LOUT, ROUT, MONOUT). Operating range 1.8 V to 3.3 V, absolute max 3.6 V; decouple locally.
12 AVDD power_in Analogue supply for the ADC/DAC and reference circuitry. Operating range 1.8 V to 3.3 V, absolute max 3.6 V; decouple locally.
13 AGND power_in Analogue ground, return path for AVDD. Must be within 0.3 V of DGND.
14 VREF passive Reference-voltage decoupling capacitor pin. Connect an external decoupling capacitor to AGND; do not load with any signal current.
15 VMID passive Mid-rail voltage decoupling capacitor pin (AVDD/2 bias). Connect an external decoupling capacitor to AGND.
16 MICINP input Positive analogue microphone input to the PGA + MIC boost front end.
17 MICINN input Negative analogue microphone input (also usable as AUXIN per the block diagram) to the PGA + MIC boost front end.
18 SDIN bidirectional Control-interface data input; also drives the 2-wire (I²C-style) acknowledge output. Open-drain during ACK phase; requires external pull-up when used in 2-wire mode.
19 SCLK input Control-interface clock input for the 2-wire (I²C-style) register interface.
20 MCLK input Master clock input. Supports 256fs/384fs or USB master clock rates (12 MHz, 24 MHz, 12.288 MHz, 24.576 MHz); sample rates 8 kHz to 96 kHz are generated internally without an external PLL.

Key specifications

Parameter Value
Manufacturer ESHINE
Package QFN4x4-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: CJC8990
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN4x4-20 (KiCad packages3D, STEP)
  • 3D model files: cjc8990-etched.step / cjc8990-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cjc8990.step / cjc8990.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ESHINE datasheet (73 pp, sha256 d9d5dd68b3ee86fc, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF