CJC1808

{
  "slug": "cjc1808",
  "version": "0.1.0",
  "type": "component",
  "description": "ESHINE Analog To Digital Converters (ADC), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "data acquisition",
    "cjc1808",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cjc1808.kicad_sym",
    "cjc1808.kicad_mod",
    "cjc1808.glb",
    "cjc1808.step",
    "cjc1808.lbr",
    "docs/hero.png",
    "docs/cjc1808-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cjc1808-hero.glb",
    "cjc1808-hero.overlay.json",
    "cjc1808-etched.glb"
  ],
  "component": {
    "mpn": "CJC1808",
    "manufacturer": "ESHINE",
    "package": "TSSOP-14",
    "pin_count": 14,
    "category": "Data Acquisition",
    "subcategory": "Analog To Digital Converters (ADC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590907407965380608",
    "parts": {
      "symbol": "cjc1808.kicad_sym",
      "footprint": "cjc1808.kicad_mod",
      "model_3d": "cjc1808-hero.glb",
      "model_3d_plain": "cjc1808-etched.glb",
      "model_3d_step": "cjc1808-etched.step",
      "model_3d_step_plain": "cjc1808.step",
      "lbr": "cjc1808.lbr"
    },
    "distributor_links": {
      "lcsc": "C7431494"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T11:44:48Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VREF",
        "type": "power_in",
        "description": "Reference-voltage decoupling pin held at 1/2 VCC (center voltage 0.5 VCC), to be bypassed to AGND with 0.1 µF ceramic and 10 µF electrolytic capacitors placed as close to the pin as possible."
      },
      {
        "number": "2",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground, which must be tied directly to DGND under the package with low impedance to limit digital noise feeding into the analog ground."
      },
      {
        "number": "3",
        "name": "VCC",
        "type": "power_in",
        "description": "Analog power supply at 3.3 V nominal, with a recommended range of 2.7 V to 5.5 V and an absolute maximum of 5.5 V."
      },
      {
        "number": "4",
        "name": "VDD",
        "type": "power_in",
        "description": "Digital power supply at 3.3 V nominal, with a recommended range of 2.7 V to 3.6 V and an absolute maximum of 4 V."
      },
      {
        "number": "5",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground, which must be tied directly to AGND under the package with low impedance to reduce noise coupling."
      },
      {
        "number": "6",
        "name": "SCKI",
        "type": "input",
        "description": "System clock input that must be 256 fs, 384 fs or 512 fs (2.048 MHz to 49.152 MHz), with CMOS input levels of VIH 2 V min and VIL 0.8 V max and an absolute maximum of 5.5 V."
      },
      {
        "number": "7",
        "name": "LRCK",
        "type": "bidirectional",
        "description": "Audio-data latch-enable (word clock) that is an input in slave mode and an output in master mode, operating over sampling rates of 8 kHz to 96 kHz."
      },
      {
        "number": "8",
        "name": "BCK",
        "type": "bidirectional",
        "description": "Audio bit clock that is an input in slave mode (64 or 48 BCK per frame) and an output in master mode at 64 BCK per frame."
      },
      {
        "number": "9",
        "name": "DOUT",
        "type": "output",
        "description": "Audio-data digital output (MSB-first, 2's complement) with VOH of 2.8 V min at -4 mA and VOL of 0.5 V max at 4 mA, and a recommended load capacitance of 20 pF; it is forced to zero during clock-halt reset."
      },
      {
        "number": "10",
        "name": "MD0",
        "type": "input",
        "description": "Audio-interface mode select bit 0, which together with MD1 selects slave or master mode and the system clock ratio per Table 2 and must be set before power-on; digital input with VIH 2 V min and VIL 0.8 V max."
      },
      {
        "number": "11",
        "name": "MD1",
        "type": "input",
        "description": "Audio-interface mode select bit 1, which together with MD0 selects slave or master mode and the system clock ratio per Table 2 and must be set before power-on; digital input with VIH 2 V min and VIL 0.8 V max."
      },
      {
        "number": "12",
        "name": "FMT",
        "type": "input",
        "description": "Audio-interface format select, where Low selects I2S 24-bit and High selects left-justified 24-bit; digital input with VIH 2 V min and VIL 0.8 V max."
      },
      {
        "number": "13",
        "name": "VINL",
        "type": "input",
        "description": "Single-ended analog input for the left channel, with full scale of 1.98 Vpp (0 dB), an input range of 0.6 VCC Vpp, and an absolute maximum of -0.3 V to (VCC + 0.3 V) and below 5.5 V."
      },
      {
        "number": "14",
        "name": "VINR",
        "type": "input",
        "description": "Single-ended analog input for the right channel, with full scale of 1.98 Vpp (0 dB), an input range of 0.6 VCC Vpp, and an absolute maximum of -0.3 V to (VCC + 0.3 V) and below 5.5 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin-number-to-position mapping (pin 1 orientation and left/right side layout) is only given in t; The VREF pin type is set to passive because the datasheet only labels it as a reference-voltage deco; LRCK and BCK are marked I/O in the datasheet and act as inputs in slave mode and outputs in master m"
        ],
        "pages_sent": 21,
        "cost_usd": 0.0659,
        "at": "2026-10-18T11:41:13"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590907407965380608",
        "pages": 21,
        "sha256": "18f98ee3d2ded2d9",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cjc1808.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.0
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3ee5786aae56190997aa793ba3cfc003fd616782770e29719b4562f012982245",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cjc1808-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.0
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3e5ac5813bac975704093db4970854de32fb45aa9fde32d9cae5bcd3f03de30a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}