# CJC1808

**ESHINE** · Analog To Digital Converters (ADC) · TSSOP-14

CJC1808 from ESHINE, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Reference-voltage decoupling pin held at 1/2 VCC (center voltage 0.5 VCC), to be bypassed to AGND with 0.1 µF ceramic and 10 µF electrolytic capacitors placed as close to the pin as possible. |
| 2 | AGND | power_in | Analog ground, which must be tied directly to DGND under the package with low impedance to limit digital noise feeding into the analog ground. |
| 3 | VCC | power_in | Analog power supply at 3.3 V nominal, with a recommended range of 2.7 V to 5.5 V and an absolute maximum of 5.5 V. |
| 4 | VDD | power_in | Digital power supply at 3.3 V nominal, with a recommended range of 2.7 V to 3.6 V and an absolute maximum of 4 V. |
| 5 | DGND | power_in | Digital ground, which must be tied directly to AGND under the package with low impedance to reduce noise coupling. |
| 6 | SCKI | input | System clock input that must be 256 fs, 384 fs or 512 fs (2.048 MHz to 49.152 MHz), with CMOS input levels of VIH 2 V min and VIL 0.8 V max and an absolute maximum of 5.5 V. |
| 7 | LRCK | bidirectional | Audio-data latch-enable (word clock) that is an input in slave mode and an output in master mode, operating over sampling rates of 8 kHz to 96 kHz. |
| 8 | BCK | bidirectional | Audio bit clock that is an input in slave mode (64 or 48 BCK per frame) and an output in master mode at 64 BCK per frame. |
| 9 | DOUT | output | Audio-data digital output (MSB-first, 2's complement) with VOH of 2.8 V min at -4 mA and VOL of 0.5 V max at 4 mA, and a recommended load capacitance of 20 pF; it is forced to zero during clock-halt reset. |
| 10 | MD0 | input | Audio-interface mode select bit 0, which together with MD1 selects slave or master mode and the system clock ratio per Table 2 and must be set before power-on; digital input with VIH 2 V min and VIL 0.8 V max. |
| 11 | MD1 | input | Audio-interface mode select bit 1, which together with MD0 selects slave or master mode and the system clock ratio per Table 2 and must be set before power-on; digital input with VIH 2 V min and VIL 0.8 V max. |
| 12 | FMT | input | Audio-interface format select, where Low selects I2S 24-bit and High selects left-justified 24-bit; digital input with VIH 2 V min and VIL 0.8 V max. |
| 13 | VINL | input | Single-ended analog input for the left channel, with full scale of 1.98 Vpp (0 dB), an input range of 0.6 VCC Vpp, and an absolute maximum of -0.3 V to (VCC + 0.3 V) and below 5.5 V. |
| 14 | VINR | input | Single-ended analog input for the right channel, with full scale of 1.98 Vpp (0 dB), an input range of 0.6 VCC Vpp, and an absolute maximum of -0.3 V to (VCC + 0.3 V) and below 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ESHINE |
| Package | TSSOP-14 |
| Category | Data Acquisition |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC Analog supply voltage (absolute maximum) | VCC | -0.3 |  | 5.5 | V |  | 5 |
| VDD Digital supply voltage (absolute maximum) | VDD | -0.3 |  | 4 | V |  | 5 |
| Ground voltage differences AGND, DGND |  | -0.1 |  | 0.1 | V |  | 5 |
| Digital input voltage LRCK, BCK, DOUT |  | -0.3 |  |  | V | max printed as (VDD+0.3 V)<4 V | 5 |
| Digital input voltage SCKI, MD0, MD1, FMT |  | -0.3 |  | 5.5 | V |  | 5 |
| Analog input voltage VINL, VINR, VREF |  | -0.3 |  |  | V | max printed as (VCC+0.3 V)<5.5 V | 5 |
| Input current (any pins except supplies) |  | -10 |  | 10 | mA |  | 5 |
| Junction temperature | TJ |  |  | 125 | °C |  | 5 |
| Storage temperature | Tstg | -55 |  | 125 | °C |  | 5 |
| VCC Analog supply voltage (recommended) | VCC | 2.7 | 3.3 | 5.5 | V |  | 6 |
| VDD Digital supply voltage (recommended) | VDD | 2.7 | 3.3 | 3.6 | V |  | 6 |
| High input logic level (recommended) | VIH | 2 |  |  | V | max printed as VDD | 6 |
| Low input logic level (recommended) | VIL | 0 |  | 0.8 | V |  | 6 |
| Digital input clock frequency, system clock |  | 2.048 |  | 49.152 | MHz |  | 6 |
| Digital input clock frequency, sampling clock |  | 8 |  | 96 | kHz |  | 6 |
| Operating ambient temperature range | TA |  |  | 85 | °C |  | 6 |
| Junction temperature (recommended) | TJ | -55 |  | 125 | °C |  | 6 |
| Sampling frequency fs | fs | 8 | 48 | 96 | kHz |  | 6 |
| System clock frequency 256 fs |  | 2.048 | 12.288 | 24.576 | MHz |  | 6 |
| System clock frequency 384 fs |  | 3.072 | 18.432 | 36.864 | MHz |  | 6 |
| System clock frequency 512 fs |  | 4.096 | 24.576 | 49.152 | MHz |  | 6 |
| High input logic level | VIH | 2 |  |  | V | max printed as VDD | 6 |
| Low input logic level | VIL | 0 |  | 0.8 | V |  | 6 |
| High input logic current | IIH | -10 |  | 10 | µA |  | 6 |
| Low input logic current | IIL | -10 |  | 10 | µA |  | 6 |
| High output logic level | VOH | 2.8 |  |  | V | IOUT = -4 mA | 6 |
| Low output logic level | VOL |  |  | 0.5 | V | IOUT = 4 mA | 6 |
| Pass-band ripple |  | -0.035 |  | 0.035 | dB |  | 7 |
| System clock pulse duration, HIGH | tw(SCKH) | 8 |  |  | ns |  | 8 |
| System clock pulse duration, LOW | tw(SCKL) | 8 |  |  | ns |  | 8 |
| System clock duty cycle |  | 45 |  | 55 | % |  | 8 |
| Delay time from SCKI halt to internal reset | t(CKR) | 4 |  |  | µs |  | 8 |
| LRCK setup time to BCK rising edge (slave) | t(LRSU) | 50 |  |  | ns |  | 8 |
| LRCK hold time to BCK rising edge (slave) | t(LRHD) | 10 |  |  | ns |  | 8 |
| Delay time, BCK falling edge to DOUT valid (slave) | t(CKDO) | -10 |  | 40 | ns |  | 8 |
| Delay time, LRCK edge to DOUT valid (slave) | t(LRDO) | -10 |  | 40 | ns |  | 8 |
| BCK period (master) | t(BCKP) | 150 |  | 2000 | ns |  | 8 |
| BCK pulse duration, HIGH (master) | t(BCKH) | 65 |  | 1200 | ns |  | 8 |
| BCK pulse duration, LOW (master) | t(BCKL) | 65 |  | 1200 | ns |  | 8 |
| Delay time, BCK falling edge to LRCK valid (master) | t(CKLR) | -10 |  | 20 | ns |  | 8 |
| LRCK period (master) | t(LRCP) | 10 |  | 125 | ns |  | 8 |
| Delay time, BCK falling edge to DOUT valid (master) | t(CKDO) | -10 |  | 20 | ns |  | 8 |
| Delay time, LRCK edge to DOUT valid (master) | t(LRDO) | -10 |  | 20 | ns |  | 8 |
| Delay time, SCKI rising edge to BCK edge | t(SCKBCK) | 5 |  | 30 | ns |  | 8 |

## CAD (KiCad official)

- Symbol: `CJC1808`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `cjc1808-etched.step` / `cjc1808-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cjc1808.step` / `cjc1808.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ESHINE datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590907407965380608) (21 pp, sha256 `18f98ee3d2ded2d9`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cjc1808-datasheet.pdf)