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CJA03N10S

Changjing · MOSFETs · SOT-89-3L

CJA03N10S from Changjing, in a SOT-89-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GATE input Gate terminal of the N-channel MOSFET, rated for a gate-source voltage VGS of ±20 V per the maximum ratings.
2 DRAIN passive Drain terminal of the MOSFET, rated for 100 V drain-source voltage with 3 A continuous drain current and 20 A pulsed drain current.
3 SOURCE passive Source terminal of the MOSFET, serving as the reference for the ±20 V gate-source rating.

Key specifications

Parameter Value
Manufacturer Changjing
Package SOT-89-3L
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: CJA03N10S
  • Footprint: Package_TO_SOT_SMD:SOT-89-3
  • 3D model: SOT-89-3L (KiCad packages3D, STEP)
  • 3D model files: cja03n10s-etched.step / cja03n10s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cja03n10s.step / cja03n10s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Changjing datasheet (5 pp, sha256 ec93184efd126222, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF