# CJ6101B33M

**Changjing** · Voltage Reference · SOT-23-5L

CJ6101B33M from Changjing, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Unregulated power input, 1.8 V to 8 V (abs max 9 V). Bypass to VSS with a 1 µF ceramic capacitor close to the pin; a small series resistor (~3 Ω) may be added with an X5R ceramic to damp start-up transients. |
| 2 | VSS | power_in | Device ground / common return for VIN, VOUT and CE. All voltages in the datasheet are referenced to this node. |
| 3 | CE | input | Chip-enable logic input. On the 'B' option (CJ6101B) it is active-high with an internal pull-down resistor to VSS and an internal output-discharge resistor on VOUT, so leaving CE open keeps the regulator off. VCE(H) ≥ 1.5 V (up to VIN) enables the regulator; VCE(L) ≤ 0.3 V disables it (standby current ≈ 0.1 µA). |
| 4 | NC | unconnected | No internal connection. Leave floating or tie to VSS; do not use as a routing via. |
| 5 | VOUT | power_out | Regulated 3.3 V output, up to 300 mA continuous (600 mA absolute-max). Requires a 1 µF ceramic (or tantalum) capacitor to VSS close to the pin for loop stability; typical dropout is 110 mV at 100 mA and output noise ≈ 27 × VOUT µVRMS (10 Hz-100 kHz). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Changjing |
| Package | SOT-23-5L |
| Category | PMIC |
| Pins | 5 |

## Ordering variants

Same part, different packaging or reel option.

- `CJ6101B33MM`
- `CJ6101B33MP`
- `CJ6101B33MF`

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | -0.3 |  | 9 | V |  | 2 |
| Output Voltage | VOUT | -0.3 |  |  | V |  | 2 |
| Output Current | IOUT |  |  | 600 | mA |  | 2 |
| Operating Ambient Temperature Range | TA | -40 |  | 85 | °C |  | 2 |
| Storage Temperature | Tstg | -40 |  | 125 | °C |  | 2 |
| Soldering Temperature | Tsolder |  |  | 260 |  | 10s | 2 |
| Operating Junction Temperature Range | Tj | -40 |  | 125 | °C |  | 2 |
| Supply voltage at VIN | VIN | 1.8 |  | 8 | V |  | 3 |
| Operating junction temperature range | Tj | -40 |  | 125 | °C |  | 3 |
| Operating free air temperature range | TA | -40 |  | 85 | °C |  | 3 |
| Input Voltage | VIN | 1.8 |  | 8 | V |  | 3 |
| Output Voltage Range | VOUT | 1.2 |  | 5 | V |  | 3 |
| DC Output Accuracy |  | -2 |  | 2 | % | IOUT=1mA | 3 |
| DC Output Accuracy |  | -1 |  | 1 | % | IOUT=1mA | 3 |
| Supply Current | ISS | 0.6 | 0.7 | 1.3 | μA | IOUT=0, 1.2V≤VOUT≤3.3V | 3 |
| Line Regulation | ∆VOUT/(VOUT×∆VIN) |  | 0.05 | 0.3 | %/V | IOUT =10mA, VOUT +1V≤VIN≤8V | 3 |
| Output Current Limit | ILIM | 550 | 700 | 850 | mA | VOUT= 0.5 x VOUT(Normal) , VIN = 5V | 3 |
| CE "High" Voltage | VCE“H” | 1.5 |  |  | V |  | 3 |
| CE "Low" Voltage | VCE“L” |  |  | 0.3 | V |  | 3 |

## CAD (KiCad official)

- Symbol: `CJ6101B33M`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5L (KiCad packages3D, STEP)
- 3D model files: `cj6101b33m-etched.step` / `cj6101b33m-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cj6101b33m.step` / `cj6101b33m.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Changjing datasheet](docs/cj6101b33m-datasheet.pdf) (10 pp, sha256 `0e2340656a2045f6`, retrieved 2026-08-17, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cj6101b33m-datasheet.pdf)