component
CJ502K
Public Made by Adomby adom
Changjing MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CJ502K
Changjing · MOSFETs · SOT-23
CJ502K from Changjing, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GATE | input | Gate terminal of the P-channel MOSFET; gate-source voltage is rated at ±20 V, and a protection diode is built in between gate and source. |
| 2 | SOURCE | passive | Source terminal, the reference for VGS (±20 V); the source-drain diode is rated at -0.18 A continuous and -0.7 A pulsed. |
| 3 | DRAIN | passive | Drain terminal; drain-source voltage is rated at -50 V, with continuous drain current of -0.18 A and pulsed drain current of -0.7 A (tp < 10 µs). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Changjing |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | -50 | V | 1 | |||
| Gate-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Continuous Drain Current (note 1) | ID | -0.18 | A | Note 1: FR4 PCB, single-sided copper, tin-plated, mounting pad for drain 1 cm2 | 1 | ||
| Pulsed Drain Current | IDM | -0.7 | A | tp <10 μs | 1 | ||
| Power Dissipation (note 2) | 350 | mW | Note 2: FR4 PCB, single-sided copper, tin-plated and standard footprint | 1 | |||
| Power Dissipation (note 1) | PD | 420 | mW | Note 1: FR4 PCB, single-sided copper, tin-plated, mounting pad for drain 1 cm2 | 1 | ||
| Thermal Resistance from Junction to Ambient (note 2) | 357 | ℃/W | Note 2: FR4 PCB, single-sided copper, tin-plated and standard footprint | 1 | |||
| Thermal Resistance from Junction to Ambient (note 1) | RθJA | 298 | ℃/W | Note 1: FR4 PCB, single-sided copper, tin-plated, mounting pad for drain 1 cm2 | 1 | ||
| Junction Temperature | TJ | 150 | ℃ | 1 | |||
| Storage Temperature | TSTG | -55 | 150 | ℃ | 1 | ||
| Maximum Lead Temperature for Soldering Purposes | TL | 260 | ℃ | Duration for 5 seconds | 1 | ||
| Drain-source breakdown voltage | V(BR)DSS | -50 | V | VGS = 0V, ID =-250µA | 2 | ||
| Zero gate voltage drain current | IDSS | -15 | µA | VDS =-50V, VGS = 0V | 2 | ||
| Zero gate voltage drain current | IDSS | -0.1 | µA | VDS =-25V, VGS = 0V | 2 | ||
| Gate-body leakage current | IGSS | -10 | 10 | µA | VGS =±20V, VDS = 0V | 2 | |
| Gate threshold voltage (note 1) | VGS(th) | -2 | -0.9 | V | VDS =VGS, ID =-250µA | 2 | |
| Drain-source on-resistance (note 1) | RDS(on) | 10 | Ω | VGS =-5V, ID =-0.1A | 2 | ||
| Drain-source on-resistance (note 1) | RDS(on) | 8 | Ω | VGS =-10V, ID =-0.1A | 2 | ||
| Forward transconductance (note 1) | gFS | 50 | mS | VDS=-25V; ID=-100mA | 2 | ||
| Continuous current | IS | -0.18 | A | 2 | |||
| Pulsed current | ISM | -0.7 | A | 2 | |||
| Diode forward voltage (note 1) | VDS | -2.2 | V | IS=-0.13A, VGS = 0V | 2 |
CAD (KiCad official)
- Symbol:
CJ502K - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
cj502k-etched.step/cj502k-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cj502k.step/cj502k.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Changjing datasheet (5 pp, sha256
156800c7c6699f0b, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CJ502K
**Changjing** · MOSFETs · SOT-23
CJ502K from Changjing, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GATE | input | Gate terminal of the P-channel MOSFET; gate-source voltage is rated at ±20 V, and a protection diode is built in between gate and source. |
| 2 | SOURCE | passive | Source terminal, the reference for VGS (±20 V); the source-drain diode is rated at -0.18 A continuous and -0.7 A pulsed. |
| 3 | DRAIN | passive | Drain terminal; drain-source voltage is rated at -50 V, with continuous drain current of -0.18 A and pulsed drain current of -0.7 A (tp < 10 µs). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Changjing |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | | | -50 | V | | 1 |
| Gate-Source Voltage | VGS | -20 | | 20 | V | | 1 |
| Continuous Drain Current (note 1) | ID | | | -0.18 | A | Note 1: FR4 PCB, single-sided copper, tin-plated, mounting pad for drain 1 cm2 | 1 |
| Pulsed Drain Current | IDM | | | -0.7 | A | tp <10 μs | 1 |
| Power Dissipation (note 2) | | | | 350 | mW | Note 2: FR4 PCB, single-sided copper, tin-plated and standard footprint | 1 |
| Power Dissipation (note 1) | PD | | | 420 | mW | Note 1: FR4 PCB, single-sided copper, tin-plated, mounting pad for drain 1 cm2 | 1 |
| Thermal Resistance from Junction to Ambient (note 2) | | | | 357 | ℃/W | Note 2: FR4 PCB, single-sided copper, tin-plated and standard footprint | 1 |
| Thermal Resistance from Junction to Ambient (note 1) | RθJA | | | 298 | ℃/W | Note 1: FR4 PCB, single-sided copper, tin-plated, mounting pad for drain 1 cm2 | 1 |
| Junction Temperature | TJ | | | 150 | ℃ | | 1 |
| Storage Temperature | TSTG | -55 | | 150 | ℃ | | 1 |
| Maximum Lead Temperature for Soldering Purposes | TL | | | 260 | ℃ | Duration for 5 seconds | 1 |
| Drain-source breakdown voltage | V(BR)DSS | -50 | | | V | VGS = 0V, ID =-250µA | 2 |
| Zero gate voltage drain current | IDSS | | | -15 | µA | VDS =-50V, VGS = 0V | 2 |
| Zero gate voltage drain current | IDSS | | | -0.1 | µA | VDS =-25V, VGS = 0V | 2 |
| Gate-body leakage current | IGSS | -10 | | 10 | µA | VGS =±20V, VDS = 0V | 2 |
| Gate threshold voltage (note 1) | VGS(th) | -2 | | -0.9 | V | VDS =VGS, ID =-250µA | 2 |
| Drain-source on-resistance (note 1) | RDS(on) | | | 10 | Ω | VGS =-5V, ID =-0.1A | 2 |
| Drain-source on-resistance (note 1) | RDS(on) | | | 8 | Ω | VGS =-10V, ID =-0.1A | 2 |
| Forward transconductance (note 1) | gFS | 50 | | | mS | VDS=-25V; ID=-100mA | 2 |
| Continuous current | IS | | | -0.18 | A | | 2 |
| Pulsed current | ISM | | | -0.7 | A | | 2 |
| Diode forward voltage (note 1) | VDS | | | -2.2 | V | IS=-0.13A, VGS = 0V | 2 |
## CAD (KiCad official)
- Symbol: `CJ502K`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `cj502k-etched.step` / `cj502k-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cj502k.step` / `cj502k.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Changjing datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588918261522583552) (5 pp, sha256 `156800c7c6699f0b`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cj502k-datasheet.pdf)