component
CJ4054A420M
Public Made by Adomby adom
Changjing Pre-ordered transistors, SOT-23-5L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
CJ4054A420M
Changjing · Pre-ordered transistors · SOT-23-5L
CJ4054A420M from Changjing, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CHRG | output | Open-drain charge status output that is pulled low by an internal N-channel MOSFET (about 10mA sink) while charging and is high impedance during undervoltage lockout. |
| 2 | GND | power_in | Ground terminal. |
| 3 | BAT | bidirectional | Charger power stage current output and battery voltage sense input that regulates the final float voltage (4.20V for CJ4054A420M) and should be bypassed to GND with a 10µF to 47µF capacitor, drawing less than 2µA in shutdown or sleep mode. |
| 4 | VCC | power_in | Charger positive input supply, specified from 4.5V to 6.5V and to be bypassed with at least a 4.7µF capacitor, which enters low-power sleep mode when VCC drops to within 80mV of the BAT voltage. |
| 5 | PROG | output | Charge current program, charge current monitor and shutdown pin, programmed by a 1% RPROG resistor to GND (regulated to 1V in constant-current mode and 0.1V in pre-conditioning), with a 1.21V shutdown threshold and an approximately 2.4V clamp. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Changjing |
| Package | SOT-23-5L |
| Category | Triode/MOS Tube/Transistor |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Voltage | VCC | -0.3 | 10 | V | All voltages with respect to network ground | 4 | |
| PROG Pin Voltage | -0.3 | V | Printed as -0.3~VCC+0.3; upper limit is an expression, not a number | 4 | |||
| BAT Pin Voltage | -0.3 | 8 | V | 4 | |||
| CHRG Pin Voltage | -0.3 | 10 | V | 4 | |||
| BAT Pin Output Current (Continuous) | IBAT | 800 | mA | 4 | |||
| Output sink current | ICHRG | 10 | mA | 4 | |||
| Power dissipation | PD | 400 | mW | SOT-23-5L package | 4 | ||
| Operating Ambient Temperature Range | TA | -40 | 85 | °C | 4 | ||
| Junction Temperature | TJ | -40 | 125 | °C | 4 | ||
| Storage Temperature | Tstg | -65 | 125 | °C | 4 | ||
| Lead Temperature (Soldering) | Tsolder | 260 | °C | 10s | 4 | ||
| ESD rating HBM | 4000 | V | JESD22-A114A | 4 | |||
| ESD rating MM | 200 | V | JESD22-A115A | 4 | |||
| Input voltage range | VCC | 4.5 | 6.5 | V | 4 | ||
| BAT Pin Output Current (Continuous) | IBAT | 10 | 600 | mA | Footnote 2: thermal regulation reduces current at TJ 120°C | 4 | |
| Operating junction temperature range | TJ | 0 | 70 | °C | 4 | ||
| Fast-charge current programming resistor | RPROG | 1.66 | 100 | kΩ | Use 1% tolerance metal film resistor (footnote 3) | 4 | |
| Undervoltage Lockout Threshold | VUVL | 3.9 | V | VCC Rising: 0V→4V | 5 | ||
| Hysteresis on UVLO | ΔVUVL | 150 | mV | VCC Falling: 4V→0V | 5 | ||
| Manual Shutdown Threshold Voltage (PROG pin rising) | VMSD | 1.15 | 1.21 | 1.3 | V | PROG Pin Rising | 5 |
| Manual Shutdown Threshold Voltage (PROG pin falling) | VMSD | 0.9 | 1 | 1.1 | V | PROG Pin Falling | 5 |
| Input Supply Current, Charge Mode | ICC(CHG) | 100 | 200 | µA | Charge Mode, RPROG=10kΩ | 5 | |
| Input Supply Current, Standby Mode (Charge Terminated) | ICC(STB) | 25 | 50 | µA | 5 | ||
| Input Supply Current, Shutdown Mode | ICC(SHDN) | 25 | 50 | µA | RPROG Not Connected or VCC<VUVL | 5 | |
| Input Supply Current, Sleep Mode | ICC(SLP) | 25 | 50 | µA | VUVL < VCC < VBAT + VSLP | 5 | |
| Battery leakage current into BAT pin, Standby Mode | IBAT(STB) | -2.5 | -6 | µA | Standby Mode (Charge Terminated), VBAT = VFLOAT | 5 | |
| Battery leakage current into BAT pin, Shutdown Mode | IBAT(SHDN) | -2 | 1 | 2 | µA | Shutdown Mode (RPROG Not Connected or VCC<VUVL) | 5 |
| Battery leakage current into BAT pin, Sleep Mode | IBAT(SLP) | -2 | 1 | 2 | µA | Sleep Mode (VUVL < VCC < VBAT + VSLP or VCC Floating) | 5 |
| Regulated Output Voltage Accuracy | VFLOAT | -50 | 50 | mV | 0°C ≤ TA ≤ 85°C, IBAT = 20mA, RPROG=10kΩ | 5 | |
| Dropout voltage, VCC, VBAT | V(DO) | 240 | mV | IBAT=600mA | 5 | ||
| Fast-Charge Current Range | ICHG | 10 | 600 | mA | VBAT > VTRIKL, ICHG= KPROG x VPROG /RPROG | 5 | |
| Fast-Charge Current Set Voltage | VPROG | 0.9 | 1 | 1.1 | V | RPROG = 10kΩ, Current Mode | 5 |
| Fast-Charge Current set factor | KPROG | 1000 | mA ∗ kΩ / Volts | 100mA≤ICHG≤600mA | 5 | ||
| External resistor range | RPROG | 1.66 | 100 | kΩ | Resistor connected to PROG pin | 5 | |
| Fast-Charge Current in typical application | ICHG | 450 | 500 | 550 | mA | RPROG = 2kΩ, VBAT=4.0V, Current Regulation Mode | 5 |
| Fast-Charge Current in typical application | ICHG | 90 | 100 | 110 | mA | RPROG = 10kΩ, VBAT=4.0V, Current Regulation Mode | 5 |
| PROG Pin Pull-Up Current | IPROG | 0.15 | A | 5 | |||
| Pre-charge to fast-charge transition threshold | VTRIKL | 2.9 | V | RPROG = 10kΩ, VBAT Rising | 6 | ||
| Pre-charge Hysteresis | V(TRIKL-HYS) | 100 | mV | RPROG = 10kΩ, VBAT Falling | 6 | ||
| Pre-charge Current range | I(PRECHG) | 0.3 | 70 | mA | VBAT < VTRIKL, I(PRECHG)= KPROG x VPRECHG /RPROG | 6 | |
| Pre-charge Current set voltage | VPRECHG | 100 | mV | Voltage on PROG pin, VBAT < VTRIKL | 6 | ||
| Pre-charge Current in typical application | I(PRECHG) | 50 | mA | VBAT < VTRIKL, RPROG=2kΩ | 6 | ||
| Battery shorted regulation current | IBAT(SHORT) | 50 | mA | BAT=GND, RPROG=2kΩ | 6 | ||
| Temperature regulation limit | TJ(REG) | 120 | °C | VCC= 5V, VBAT=3.2 V, Fast-charge current set to 600mA | 6 | ||
| C/10 Charge termination detection current range | ITERM | 1 | 70 | mA | VBAT > VRECHG, ITERM= KPROG x VTERM /RPROG | 6 | |
| C/10 Charge termination detection set voltage | VTERM | 100 | mV | VBAT > VRECHG | 6 | ||
| C/10 Charge termination detection in typical application | ITERM | 50 | mA | RPROG=2kΩ | 6 | ||
| C/10 Charge termination detection current | ITERM | 7 | 10 | 13 | mA | RPROG=10kΩ | 6 |
| Deglitch time, termination detected | TDGL(TERM) | 0.8 | 1.8 | 4 | mS | IBAT Falling Below ICHG/10 | 6 |
| Recharge Threshold Detection | ΔVRECHG | 150 | mV | VFLOAT-VBAT < ΔVRECHG | 6 | ||
| Deglitch time, recharge detection | TDGL(RECHG) | 0.8 | 1.8 | 4 | mS | VBAT Falling | 6 |
| Sleep mode entry threshold voltage | VSLP | 80 | mV | VCC Falling, VUVL < VBAT ≤ VFLOAT | 6 | ||
| Sleep mode exit threshold voltage | V(SLP_EXIT) | 100 | mV | VCC Rising, VUVL < VBAT ≤ VFLOAT | 6 | ||
| CHRG Pin Low-level Output Voltage | VCHRG | 0.3 | 0.6 | V | ICHRG=5mA (sink current) | 6 | |
| Soft-Start Time | tSS | 20 | µs | IBAT=0 to IBAT =1000V/RPROG | 6 | ||
| Junction-to-ambient thermal resistance, topside copper 2500mm2 | θJA | 125 | °C/W | 2-layer board, backside copper 2500mm2, board area 2500mm2, still air | 16 | ||
| Junction-to-ambient thermal resistance, topside copper 1000mm2 | θJA | 125 | °C/W | 2-layer board, backside copper 2500mm2, board area 2500mm2, still air | 16 | ||
| Junction-to-ambient thermal resistance, topside copper 225mm2 | θJA | 130 | °C/W | 2-layer board, backside copper 2500mm2, board area 2500mm2, still air | 16 | ||
| Junction-to-ambient thermal resistance, topside copper 100mm2 | θJA | 135 | °C/W | 2-layer board, backside copper 2500mm2, board area 2500mm2, still air | 16 | ||
| Junction-to-ambient thermal resistance, topside copper 50mm2 | θJA | 150 | °C/W | 2-layer board, backside copper 2500mm2, board area 2500mm2, still air | 16 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | die to the copper lead frame, through the package leads, (especially the ground lead) to the PC board | 16 |
CAD (KiCad official)
- Symbol:
CJ4054A420M - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5L, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.15 mm tall, datasheet A, midpoint of min and max). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
- 3D model files:
cj4054a420m-etched.step/cj4054a420m-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cj4054a420m.step/cj4054a420m.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Changjing datasheet (33 pp, sha256
96f60dc73e5facbc, retrieved 2026-11-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).