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CH9350L

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WCH Jiangsu Qin Heng USB Converters, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CH9350L

WCH Jiangsu Qin Heng · USB Converters · LQFP-48(7x7)

CH9350L from WCH Jiangsu Qin Heng, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LED1 output Port 1 (DP/DM) device connection and communication indicator, high by default and driven low once the device is enumerated (lower-machine mode) or the host is initialized (upper-machine mode), 3.3V output level.
2 LED2 output Port 2 (HP/HM) device connection and communication indicator, high by default and driven low once the device is enumerated or the host is initialized, 3.3V output level.
3 RST input External reset input, active high; a high pulse of about 100ns typical resets the chip.
4 S0 input Work-state configuration pin (with S1), input with internal pull-up; S1
5 S1 input Work-state configuration pin (with S0), input with internal pull-up; see S0 for the state-selection truth table.
6 xOSC input External clock enable pin, active low; when enabled, an external 12 MHz clock must be supplied.
7 DEBUG output Reserved test pin; leave unconnected.
8 NC unconnected Reserved pin, must be left unconnected.
9 NC unconnected Reserved pin, must be left unconnected.
10 NC unconnected Reserved pin, must be left unconnected.
11 NC unconnected Reserved pin, must be left unconnected.
12 NC unconnected Reserved pin, must be left unconnected.
13 NC unconnected Reserved pin, must be left unconnected.
14 NC unconnected Reserved pin, must be left unconnected.
15 NC unconnected Reserved pin, must be left unconnected.
16 XI passive Reserved crystal oscillator input; leave floating or use the reserved pad, as the datasheet says it is not needed since the chip has an internal clock.
17 XO passive Reserved crystal oscillator inverting output; leave floating.
18 VSS/GND power_in Common ground for the device.
19 NC unconnected Reserved pin, must be left unconnected.
20 NC unconnected Reserved pin, must be left unconnected.
21 IO1 bidirectional Status synchronization pin; output in upper-machine mode (state 1) and input in lower-machine mode, following the IO1/IO2 pairing rule.
22 IO2 bidirectional Status synchronization pin; input in lower-machine mode and output in upper-machine mode, paired with IO1.
23 IO3 bidirectional Status synchronization pin; input in upper-machine mode and output in lower-machine mode (state 1 only), paired with IO4.
24 IO4 bidirectional Status synchronization pin; input in upper-machine mode and output in lower-machine mode (state 1 only), paired with IO3.
25 NC unconnected Reserved pin, must be left unconnected.
26 TNOW output Send-status output pin that can be used for RS-485 transmit direction control.
27 RXD input UART data input (serial receive).
28 TXD output UART data output (serial transmit); the default baud rate is 115200 bps, 8 data bits, 1 stop bit, no parity.
29 HP bidirectional USB D+ data line for port 2, used in lower-machine mode to connect a USB keyboard or mouse.
30 HM bidirectional USB D- data line for port 2, used in lower-machine mode to connect a USB keyboard or mouse.
31 DP bidirectional USB D+ data line for port 1; connects to the USB host in upper-machine mode and to a keyboard/mouse in lower-machine mode.
32 DM bidirectional USB D- data line; connects to the USB host as the D+/D- device side in upper-machine mode.
33 NC unconnected Reserved pin, must be left unconnected.
34 NC unconnected Reserved pin, must be left unconnected.
35 NC unconnected Reserved pin, must be left unconnected.
36 NC unconnected Reserved pin, must be left unconnected.
37 BAUD1 input Baud-rate configuration pin 1 with internal pull-up; together with BAUD0 selects 115200 (default), 57600, 38400 or 300000 bps.
38 BAUD0 input Baud-rate configuration pin 0 with internal pull-up; together with BAUD1 selects the UART baud rate.
39 NC unconnected Reserved pin, must be left unconnected.
40 NC unconnected Reserved pin, must be left unconnected.
41 VIN5 power_in External 5V supply input to the internal 5V-to-3.3V regulator; requires a 0.1uF decoupling capacitor. Absolute maximum 5.6V.
42 VDD33 power_out Internal regulator output and 3.3V internal supply input; connect to VIN5 when the supply is below 3.6V, otherwise add a 3.3uF decoupling capacitor.
43 NC unconnected Reserved pin, must be left unconnected.
44 NC unconnected Reserved pin, must be left unconnected.
45 SEL input Operating-mode select with internal pull-up: high selects lower-machine mode (default), low selects upper-machine mode; must not exceed 3.6V.
46 NC unconnected Reserved pin, must be left unconnected.
47 NC unconnected Reserved pin, must be left unconnected.
48 LED0 output Status indicator pin, high by default; low in upper-machine mode until communication with the PC succeeds, 3.3V output level.

Key specifications

Parameter Value
Manufacturer WCH Jiangsu Qin Heng
Package LQFP-48(7x7)
Category Interface
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating ambient temperature TA -40 85 ℃ VIN5=5V or VIN5=VDD33=3.3V 5
Storage ambient temperature TS -55 125 ℃ 5
Internal operating supply voltage (VDD33) VDD33 -0.4 3.6 V 5
External input supply voltage (VIN5) VIN5 -0.4 5.6 V 5
External input supply voltage (VIN5), VDD33 pin only externally capacitor-decoupled VIN5 3.6 5 5.5 V TA=25℃, VIN5=5V; excludes USB bus pins; VDD33 pin only external capacitor 5
External input supply voltage (VIN5), VDD33 pin connected to VIN5 VIN5 3 3.3 3.6 V TA=25℃, VIN5=5V; excludes USB bus pins; VDD33 pin connected to VIN5 5
Low-level input voltage VIL -0.4 0.8 V TA=25℃, VIN5=5V; excludes USB bus pins 5
High-level input voltage (max printed as VDD33+0.4 V, not a number) VIH 2 V TA=25℃, VIN5=5V; excludes USB bus pins 5
Low-level output voltage VOL 0.4 V 4mA sink current; TA=25℃, VIN5=5V; excludes USB bus pins 5
Power-on reset voltage threshold Vpot 2.2 2.4 2.5 V 5
SEL input voltage (must not exceed) SEL 3.6 V SEL pin input voltage 7
External reset (RST) active high pulse width RST 100 ns RST high level; effective reset pulse width 7

CAD (KiCad official)

  • Symbol: CH9350L
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ch9350l-etched.step / ch9350l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch9350l.step / ch9350l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WCH Jiangsu Qin Heng datasheet (16 pp, sha256 a76d148e4eb701d2, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF