component
CH9101N
Public Made by Adomby adom
WCH Jiangsu Qin Heng USB Converters, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCH9101N
WCH Jiangsu Qin Heng · USB Converters · SOP-8
CH9101N from WCH Jiangsu Qin Heng, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Common ground for the device, which must be connected to the USB bus ground. |
| 2 | TXD | output | UART serial data output, idle high. |
| 3 | VIO | power_in | I/O port supply input for the UART pins, supporting 1.8 V to 5 V, which should share the MCU supply; requires an external decoupling capacitor. |
| 4 | RXD | input | UART serial data input, idle high, with an internal pull-up resistor. |
| 5 | UD+ | bidirectional | USB D+ data line connected directly to the USB bus; no series resistor may be added. |
| 6 | UD- | bidirectional | USB D- data line connected directly to the USB bus; no series resistor may be added. |
| 7 | VDD5 | power_in | Positive supply input to the internal regulator, requiring an external decoupling capacitor; 4.0 V to 5.5 V when V3 is not tied to VDD5. |
| 8 | V3 | power_out | Internal regulator output and supply for the core and USB transceiver; tie to VDD5 for 3.0 V to 3.6 V operation, otherwise decouple with an external capacitor (about 0.1 uF). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | WCH Jiangsu Qin Heng |
| Package | SOP-8 |
| Category | Interface |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating ambient temperature | TA | -40 | 85 | ℃ | Working ambient temperature | 6 | |
| Storage ambient temperature | TS | -55 | 125 | ℃ | Storage ambient temperature | 6 | |
| USB supply voltage (VDD5 pin) | VDD5 | -0.5 | 6 | V | VDD5 pin powered, GND pin grounded | 6 | |
| Serial I/O supply voltage (VIO pin) | VIO | -0.5 | 6 | V | VIO pin powered, GND pin grounded | 6 | |
| Voltage on USB signal pins | VUSB | -0.5 | V | Printed maximum is V3+0.5 V (not numeric); max left null | 6 | ||
| Voltage on serial and other pins | VUART | -0.5 | V | Printed maximum is VIO+0.5 V (not numeric); max left null | 6 | ||
| USB supply voltage, V3 not tied to VDD5 | VDD5 | 4 | 5 | 5.5 | V | TA=25°C, VDD5=5V or VDD5=V3=3.3V, VIO=1.8V~5V; V3 not connected to VDD5, V3 with capacitor | 6 |
| USB supply voltage, V3 tied to VDD5 | VDD5 | 3 | 3.3 | 3.6 | V | TA=25°C, VDD5=5V or VDD5=V3=3.3V, VIO=1.8V~5V; V3 pin connected to VDD5, VDD5=V3 | 6 |
| Serial and other I/O supply voltage | VIO | 1.7 | 5 | 5.5 | V | TA=25°C, VDD5=5V or VDD5=V3=3.3V, VIO=1.8V~5V | 6 |
| Operating supply current, VDD5 or V3 | IVDD | 3 | 15 | mA | TA=25°C, VDD5=5V or VDD5=V3=3.3V, VIO=1.8V~5V; printed as '3 15', column assignment uncertain | 6 | |
| Operating VIO supply current (depends on I/O load) | IVIO | 0 | mA | TA=25°C, VDD5=5V or VDD5=V3=3.3V, VIO=1.8V~5V; depends on I/O load; printed typical (10) in parentheses not placed | 6 | ||
| USB suspend supply current, VDD5=5V | ISLP | 0.09 | 0.16 | mA | TA=25°C, VDD5 supply=5V, VIO=1.8V~5V; USB suspend | 6 | |
| USB suspend supply current, VDD5=V3=3.3V | ISLP | 0.085 | 0.15 | mA | TA=25°C, VDD5=V3 supply=3.3V, VIO=1.8V~5V; USB suspend | 6 | |
| USB suspend supply current, VIO supply | ISLP | 0.002 | 0.05 | mA | TA=25°C, VIO supply, no I/O load/pull-up; USB suspend | 6 | |
| Low-level input voltage | VIL | 0 | 1.5 | V | VIO=5V | 6 | |
| Low-level input voltage | VIL | 0 | 0.9 | V | VIO=3.3V | 6 | |
| Low-level input voltage | VIL | 0 | 0.5 | V | VIO=1.8V | 6 | |
| High-level input voltage | VIH | 2.5 | V | VIO=5V; printed maximum is VIO (not numeric), max left null | 6 | ||
| High-level input voltage | VIH | 1.9 | V | VIO=3.3V; printed maximum is VIO (not numeric), max left null | 6 | ||
| High-level input voltage | VIH | 1.3 | V | VIO=1.8V; printed maximum is VIO (not numeric), max left null | 6 | ||
| Low-level output voltage | VOL | 0.4 | 0.5 | V | VIO=5V, sinking 15mA | 6 | |
| Low-level output voltage | VOL | 0.3 | 0.4 | V | VIO=3.3V, sinking 8mA | 6 | |
| Pull-up current of serial and RESET pins (pulled up to VIO) | IPUP | 35 | 150 | 220 | uA | VIO=5V | 6 |
| Pull-up current of serial and RESET pins (pulled up to VIO) | IPUP | 15 | 60 | 90 | uA | VIO=3.3V | 6 |
| Pull-up current of serial and RESET pins (pulled up to VIO) | IPUP | 3 | 14 | 21 | uA | VIO=1.8V | 6 |
| V3 power-on/low-voltage reset threshold | VRV3 | 2.5 | 2.7 | 2.9 | V | V3 power-on / low-voltage reset threshold | 6 |
| VIO low-voltage reset threshold | VRVIO | 0.8 | 1 | 1.15 | V | VIO supply low-voltage reset threshold | 6 |
| HBM ESD withstand on USB or I/O pins | VESD | 5 | KV | HBM; printed '5 6' with column assignment uncertain, 6 not placed | 6 | ||
| Internal clock error (frequency/baud error) | FD | -1 | 1 | % | TA=-15°C~60°C; printed typical ±0.5 not placed as numeric | 6 | |
| Internal clock error (frequency/baud error) | FD | -1.5 | 1.5 | % | TA=-40°C~85°C; printed typical ±0.8 not placed as numeric | 6 | |
| Reset delay after power-on or external reset | TRSTD | 9 | 15 | 25 | mS | Power-on or external reset input | 7 |
| External RESET input valid pulse width | TRI | 100 | nS | RESET external reset input valid signal width | 7 | ||
| USB auto-suspend detection time | TSUSP | 3 | 5 | 9 | mS | Detection of USB automatic suspend | 7 |
| Wake-up completion time after sleep | TWAKE | 1.2 | 1.5 | 5 | uS | After chip sleep | 7 |
CAD (KiCad official)
- Symbol:
CH9101N - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
ch9101n-etched.step/ch9101n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ch9101n.step/ch9101n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: WCH Jiangsu Qin Heng datasheet (8 pp, sha256
56f3f6ae260d9731, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).